NL160120AC27_22B NEC, NL160120AC27_22B Datasheet - Page 12

• Manufacturer Part Number: NL160120AC27_22B
• Description: Display Module
• Manufacturer: NEC

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4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
4.4.2 Inverter
VDD
Note1
LVDS signals *1,*2
Note2
CS, SDATI, SCLK
Note2
Note1: In terms of voltage variation (voltage drop) while VDD rising edge is below 10.8V, a protection
Note2: LVDS signals and CS, SDATI, SCLK must be Low or High-impedance, exclude the VALID
Note3: At the beginning of the serial communication mode, take 20ms or more after the LVDS signal
Note4: The backlight should be turned on within the valid period of LVDS signals, in order to avoid
Note1: The backlight should be turned on within the valid period of LVDS signals, in order to avoid
Note2: If tr is more than 800ms, the backlight will be turned off by a protection circuit for inverter.
Note3: When VDDB is ON and BRTC is high, voltage to BRTI, BRTP and PWSEL terminals should
24.0V
22.8V
*1: DA0+/-, DA1+/-, DA2+/-, DA3+/-, CKA+/-, DB0+/-, DB1+/-, DB2+/-, DB3+/- and CKB+/-
*2: LVDS signals should be measured at the terminal of 100Ω resistance.
Voltage
0V
circuit may work, and then this product may not work.
period (See above sequence diagram), in order to avoid that internal circuits is damaged.
If some of signals are cut while this product is working, even if the signal input to it once again,
it might not work normally. VDD should be cut when the display and function signals are
stopped.
input. As writing and reading the LUT data, see “4.11 TEN-bit LOOK UP TABLE FOR
GAMMA ADJUSTMENT”.
unstable data display.
unstable data display.
be applied.
0V
0V
0V
10ms < t < 35ms
10ms < t < 35ms
tr≤800ms
PRELIMINARY DATA SHEET DOD-PP-0619 (1st edition)
10.8V
ON
0ms<t
0.1ms < Tr < 80ms
t ≥ 20ms Note3
VALID period
VALID period
VDDB
BRTC
VDD dip < 20ms
9.6V
10.8V
OFF
NL160120AC27-22B
0ms < t < 35ms
0ms<t
Toff > 200ms
Time
ON
10.8V
12
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