MX25L6402A Macronix International, MX25L6402A Datasheet - Page 6

• Manufacturer Part Number: MX25L6402A
• Description: 64M-BIT [x 1] CMOS SERIAL eLite FlashTM MEMORY
• Manufacturer: Macronix International

MX25L6402A
(5) Sector/Chip Erase
This command is sent with the sector address(A22~A16) when operating Sector Erase. The device will start the erase
sequence after CS# goes high without any further input. A sector should be erased in a typical of 2sec. The average current
is less than 26mA. The chip erase operation does not require the sector address input but two extra dummy bytes are
necessary. During this operation, customer can also access Read Status & Read ID operations.
(6) Page Program
This command is sent with the page number(A22~A7), and 128-byte page address(A6~A0), followed by programming data.
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The 128-byte page address (A6-A0) must start from 0. One to 128 bytes of data can be loaded into the buffer of the device
until CS# goes high. If the end of the page is reached, then the device will wrap around to the beginning of the page. The
device will program the specified page with buffered data(Until CS# goes high) without any further input. The typical page
program time is 2mS. The average current is less than 26mA.
During this operation, customer can also access Read Status & Read ID operations.
(7) Standby Mode
When CS# is high and there is no operation in progress, the device is put in standby mode. Typical standby current is
less than 5uA.
(8) Parallel Mode (Highly recommended for production throughputs increasing)
The parallel mode provides 8 bit outputs for increasing throughputs of factory production purpose. The parallel mode
requires 55H command code, after writing the parallel mode command and then CS# going high, after that, the eLite Flash
TM
Memory can be available to accept read/program/read status/read ID command as the normal writing command procedure.
TM
The eLite Flash
Memory will be in parallel mode until VCC power-off.
a. Only effective for Read Array, Read Status, Read ID & Page Program write data period. (refer to page 16,18,21,23)
b. For normal write command (by SI), No effect
c.Under parallel mode, the fastest access clock freq. will be changed to 1.25MHz(SCLK pin clock freq.)
d. For parallel mode, the tAA will be change to 50ns.
POWER-ON STATE
After power-up, the device is placed in the standby state with following status:
The status register is reset with following status :
Bit 7 = "1" -----> Refer to page 5 for detail.
Bit 6 = "0" -----> Device is not in parallel mode.
Bit 5,2,1 = Reserve for future use.
Bit 4 = "0" -----> Erase error flag is reset.
Bit 3 = "0" -----> Program error flag is reset.
Bit 0="1" -----> Device is in ready state.
P/N: PM1040
REV. 1.0, SEP. 29, 2004
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