MX26LV004T Macronix, MX26LV004T Datasheet
MX26LV004T
Related parts for MX26LV004T
MX26LV004T Summary of contents
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... Erase Suspend capability. - Automatically program and verify data at specified address GENERAL DESCRIPTION The MX26LV004T 4-mega bit Flash memory orga- nized as 512K bytes of 8 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. The MX26LV004T/B is packaged in 40-pin TSOP ...
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... PLCC MX26LV004T P/N:PM1099 MX26LV004T/B MX26LV004T/B PIN DESCRIPTION SYMBOL PIN NAME A0~A18 A14 Q0~Q7 A13 A11 RESET OE A10 OE CE RY/BY Q7 VCC GND 2 40 A17 39 GND A10 ...
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... BLOCK STRUCTURE Table 1: MX26LV004T SECTOR ARCHITECTURE Sector Sector Size Byte Mode SA0 64Kbytes SA1 64Kbytes SA2 64Kbytes SA3 64Kbytes SA4 64Kbytes SA5 64Kbytes SA6 64Kbytes SA7 32Kbytes SA8 8Kbytes SA9 8Kbytes SA10 16Kbytes Table 2: MX26LV004B SECTOR ARCHITECTURE Sector Sector Size Byte Mode ...
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... BLOCK DIAGRAM CONTROL CE OE INPUT WE LOGIC RESET ADDRESS LATCH A0-A18 AND BUFFER Q0-Q7 P/N:PM1099 MX26LV004T/B PROGRAM/ERASE HIGH VOLTAGE MX26LV004T/B FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 4 WRITE STATE MACHINE (WSM) STATE REGISTER COMMAND DATA DECODER ...
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... AUTOMATIC PROGRAMMING The MX26LV004T/B is byte programmable using the Au- tomatic Programming algorithm. The Automatic Pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. AUTOMATIC PROGRAMMING ALGORITHM MXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address) ...
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... TABLE 3. MX26LV004T/B AUTO SELECT MODE OPERATION Description CE Manufacturer Code Read Device ID Silicon (Top Boot Block) ID Device ID (Bottom Boot Block) NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High P/N:PM1099 MX26LV004T/B A18 A12 A13 A10 VID ...
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... Device operations are selected by writing specific ad- dress and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the TABLE 4. MX26LV004T/B COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr ...
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... TABLE 5. MX26LV004T/B BUS OPERATION DESCRIPTION CE OE Read L Write L Reset X Output Disable L Standby Vcc 0.3V NOTES: 1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4. 2. VID is the Silicon-ID-Read high voltage, 11V to 12V. 3. Refer to Table 4 for valid Data-In during a write operation. ...
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... Sequence section for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC P/N:PM1099 MX26LV004T/B Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODE When using both pins of CE and RESET, the device en- ter CMOS Standby with both pins held at Vcc 0 ...
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... However, multiplexing high volt- age onto address lines is not generally desired system design practice. The MX26LV004T/B contains a Silicon-ID-Read opera- tion to supple traditional PROM programming methodol- ogy. The operation is initiated by writing the read silicon ID command sequence into the command register. ...
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... A0 A1 Manufacture code VIL VIL Device code VIH VIL for MX26LV004T Device code VIH VIL for MX26LV004B READING ARRAY DATA The device is automatically set to reading array data after device power-up. No commands are required to re- trieve data. The device is also ready to read array data after completing an Automatic Program or Automatic Erase algorithm ...
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... The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, P/N:PM1099 MX26LV004T/B followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings ...
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... Q6:Toggle BIT I Toggle Bit indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete. Toggle P/N:PM1099 MX26LV004T/B Bit I may be read at any address, and is valid after the rising edge of the final WE or CE, whichever happens first, in the command sequence (prior to the program or erase operation), and during the sector time-out ...
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... If this time-out condition occurs during the chip erase P/N:PM1099 MX26LV004T/B operation, it specifies that the entire chip is bad or com- bination of sectors are bad. If this time-out condition occurs during the byte program- ...
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... Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits. See "Q5 : Exceeded Timing Limits" for more information. P/N:PM1099 MX26LV004T ...
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... In order to reduce power switching effect, each device should have a 0.1uF ceramic capacitor connected be- tween its VCC and GND. POWER-UP SEQUENCE The MX26LV004T/B powers up in the Read only mode. In addition, the memory contents may only be altered after successful completion of the predefined command sequences. ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. P/N:PM1099 MX26LV004T/B OPERATING RATINGS Commercial (C) Devices +150 o C ...
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... VIH max. = VCC + 1.5V for pulse width is equal to or less than VIH is over the specified maximum value, read operation cannot be guaranteed. 3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns. P/N:PM1099 MX26LV004T/B MIN. TYP MAX. ...
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... Input rise and fall times is equal to or less than 5ns. • Output load: 1 TTL gate + 100pF (Including scope and jig), for 26LV004T/B-70. 1 TTL gate + 30pF (Including scope and jig) for 26LV004T/B-55. • Reference levels for measuring timing: 1.5V. P/N:PM1099 MX26LV004T VCC = 3.0V~3.6V 26LV004T/B-55 MIN ...
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... SWITCHING TEST CIRCUITS DEVICE UNDER TEST CL=100pF Including jig capacitance for MX26LV004T/B-70 (30pF for MX26LV004T/B-55) SWITCHING TEST WAVEFORMS 3.0V INPUT 1. TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 5ns. ...
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... Figure 1. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE VIL VIH WE VIL VIH OE VIL VOH HIGH Z Outputs VOL VIH RESET VIL P/N:PM1099 MX26LV004T/B tRC ADD Valid tACC tCE tOE tOEH tACC tOH DATA Valid 21 tDF HIGH Z REV. 0.02, JUL. 12, 2004 ...
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... VCC Setup Time (Note 1) tRB Recovery Time from RY/BY tBUSY Program/Erase Valid to RY/BY Delay tBAL Sector Address Load Time NOTES: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM1099 MX26LV004T VCC = 3.0V~3.6V 26LV004T/B-55 MIN ...
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... WE Hold Time tCP CE Pulse Width tCPH CE Pulse Width High tWHWH1 Programming Operation(note2) tWHWH2 Sector Erase Operation (note2) NOTE: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. P/N:PM1099 MX26LV004T VCC = 3.0V~3.6V 26LV004T/B-55 MIN. MAX ...
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... Figure 2. COMMAND WRITE TIMING WAVEFORM VCC 3V VIH Addresses VIL tAS VIH WE VIL tOES CE VIH VIL tCS OE VIH VIL VIH Data VIL P/N:PM1099 MX26LV004T/B ADD Valid tAH tWP tCWC tCH tDS tDH DIN 24 tWPH REV. 0.02, JUL. 12, 2004 ...
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... VCC NOTES: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address P/N:PM1099 MX26LV004T/B after automatic programming starts. Device outputs DATA during programming and DATA after programming on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) Read Status Data (last two cycle) ...
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... Figure 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1099 MX26LV004T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Byte Ok ? YES No Last Address ? YES Auto Program Completed 26 REV ...
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... Data tRH RESET RY/BY NOTES: 1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device. 2.Figure indicates the last two bus cycles of the command sequence. P/N:PM1099 MX26LV004T/B PA for program SA for sector erase 555 for chip erase Data Polling tAS tAH tWHWH1 or 2 tCPH ...
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... VCC NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1099 MX26LV004T/B matic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) Read Status Data ...
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... Figure 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1099 MX26LV004T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H Data Pall from System ...
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... VCC NOTES: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status"). P/N:PM1099 MX26LV004T/B ing after automatic erase starts. Device outputs 0 dur- ing erasure and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling, timing waveform) ...
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... Figure 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1099 MX26LV004T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address NO Last Sector ...
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... WRITE OPERATION STATUS Figure 10. DATA POLLING ALGORITHM NOTE : 1.VA=Valid address for programming 2.Q7 should be re-checked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1099 MX26LV004T/B Start Read Q7~Q0 Add.=VA(1) Yes Q7 = Data ? Yes Read Q7~Q0 Add.=VA Yes Q7 = Data ? (2) No FAIL 32 Pass REV. 0.02, JUL. 12, 2004 ...
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... Figure 11. TOGGLE BIT ALGORITHM NO Program/Erase Operation Note:1.Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 change to "1". P/N:PM1099 MX26LV004T/B Start Read Q7-Q0 Read Q7-Q0 (Note 1) NO Toggle Bit Q6 = Toggle ? YES Q5= 1? YES Read Q7~Q0 Twice ...
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... WE DQ7 Q0-Q6 tBUSY RY/BY NOTES: 1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle must be toggled when DATA polling. P/N:PM1099 MX26LV004T/B VA tDF tOH Complement Complement True Status Data Status Data True ...
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... RY/BY NOTES: 1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle must be toggled when toggle bit toggling. P/N:PM1099 MX26LV004T/B VA tDF tOH Valid Status Valid Status (second read) ...
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... RY/BY Recovery Time(to CE low) Note:Not 100% tested Figure 14. RESET TIMING WAVEFORM RY/BY CE, OE RESET Reset Timing NOT during Automatic Algorithms RY/BY CE, OE RESET Reset Timing during Automatic Algorithms P/N:PM1099 MX26LV004T/B Test Setup All Speed Options Unit tRH tRP tReady2 tReady1 tRP 36 MAX 20 us MAX ...
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... VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC VIH A1 VIL ADD VIH A2-A8 A10-A18 VIL CE VIH VIL VIH WE VIL VIH OE VIL VIH DATA VIL Q0-Q7 P/N:PM1099 MX26LV004T/B tACC tCE tOE tOH DATA OUT C2H 37 tDF tOH DATA OUT B5H/B6H REV. 0.02, JUL. 12, 2004 ...
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... Input Voltage with respect to GND on ACC, OE, RESET, A9 Input Voltage with respect to GND on all power pins, Address pins, CE and WE Input Voltage with respect to GND on all I/O pins Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N:PM1099 MX26LV004T/B LIMITS MIN. TYP.(2) MAX.(3) 2.4 ...
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... ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME (ns) MX26LV004TTC-55 55 MX26LV004TTC-70 70 MX26LV004BTC-55 55 MX26LV004BTC-70 70 MX26LV004TQC-55 55 MX26LV004TQC-70 70 MX26LV004BQC-55 55 MX26LV004BQC-70 70 P/N:PM1099 MX26LV004T/B OPERATING CURRENT STANDBY CURRENT MAX.(mA) MAX.(uA PACKAGE 100 40 Pin TSOP 100 40 Pin TSOP 100 40 Pin TSOP 100 40 Pin TSOP ...
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... PACKAGE INFORMATION P/N:PM1099 MX26LV004T/B 40 REV. 0.02, JUL. 12, 2004 ...
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... P/N:PM1099 MX26LV004T/B 41 REV. 0.02, JUL. 12, 2004 ...
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... REVISION HISTORY Revision No. Description 0.01 1. Modified the erase/program cycling to 2K cycles 2. Removed data retention table 0.02 1. Modified the erase/program cycling to 2K cycles in General Description 2. Removed Protect/unprotected information 3. To added 32-PLCC package information P/N:PM1099 MX26LV004T/B Page P1,48 P48 P1 All P1,2,39,41 42 Date JUN/24/2004 JUL/12/2004 REV. 0.02, JUL. 12, 2004 ...
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... MX26LV004T/B ...