irc1802 ETC-unknow, irc1802 Datasheet - Page 3

• Manufacturer Part Number: irc1802
• Description: Vfir Mb/sec Controller Transciever
• Manufacturer: ETC-unknow

The IRC1802 is a low-cost, highly inte-
grated SIR, MIR, FIR and Very Fast Infrared
(VFIR) communications
controller capable of supporting IrDA 1.x
infrared modulation schemes including HP-
SIR and Sharp ASK. The IrDA 1.x low and
high-speed communication modes support
all speeds up to 16 Mb/s (VFIR). All
speeds can use Direct Memory Access.
The same drivers are used for all speeds
for receiving and transmitting, simplifying
driver programming and speed upgrades.
Typical applications include data transfer
in notebook computers, desktops comput-
ers, printers, access-points, digital cameras
and peer-peer or client-server network
environments.
Architecture
The IRC1802 Infrared Communications
Controller consists of an Infrared Core
module and a Host Interface module (see
IRC 1802 Block Diagram).
The Infrared Core module controls all
infrared communication functions. It is
divided into four subsystems: SIR, MIR,
FIR and Very Fast Infrared (VFIR). Each
subsystem consists of a controller and a
modem.
The SIR subsystem improves on the
popular 16550 UART scheme by combining
a high performance DMA asynchronous
receiver-transmitter with the hardware Link
Access Protocol (IrLAP) for a complete
hardware SIR packet transfer.
The Host Interface module connects to an
ISA bus or PCMCIA bus. It contains the
bus interface logic, system configuration
registers, power management circuitry, and
local DMA control functions. The IRC1802
supports two modes of block data
transfer: Host DMA and Shared Memory
Buffer. In Host DMA mode, data is
transferred using the host system’s DMA
controller. In Shared Memory mode, data
is first buffered in local RAM, then read by
the host during receive-mode or shifted
out to the infrared link during transmit-
mode.
Shared Memory and Host DMA modes
Shared Memory mode is a Local DMA
mode with 32 Kbytes SRAM locally.
In this mode, both the controller and
host have access to a shared block of
memory to which data can be read or
written. During packet transmitting or
receiving there is no data transfer on
the system bus.
For packet sending, the host copies the
packet to the Tx buffer of shared
memory, initializes the Transmit
Request and waits for the End of
Transmit, EOTR, condition to generate
an interrupt.
For packet receiving, the host waits for
the End of Receive, EOR, interrupt
condition and copies packets received
from the Rx buffer of shared memory.
The programming is simple and the
operation is fast.
Burst packet transmission and recep-
tion support for all data rates Burst
data transfer consisting of multiple IrDA
frames are accomplished by adding
control headers to the desired outgoing
data frames and arranging them
sequentially in the transmit buffer of
the host’s or local shared memory.
The Tx and Rx Frame Control Modules
control transmit and receive functions.
The 32 Kbytes shared memory can
keep seven IrDA frames with size of
2048 bytes.
Direct Interface to both Legacy
and Digital Serial Interface (SIF)
Transceivers
The Serial Interface (SIF) module allows
the controller to interface directly to
Infineon’s IRM1600
transceiver.
This transceiver supports new features
like speed mode select (VFIR), pro-
grammable modulation setting, LED
power control, receiver sensitivity and
power management.