74VHCT74AMTCX Fairchild Semiconductor, 74VHCT74AMTCX Datasheet

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74VHCT74AMTCX

Manufacturer Part Number
74VHCT74AMTCX
Description
IC FLIP FLOP DUAL D TYPE 14TSSOP
Manufacturer
Fairchild Semiconductor
Series
74VHCTr
Type
D-Typer
Datasheet

Specifications of 74VHCT74AMTCX

Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
140MHz
Delay Time - Propagation
5.8ns
Trigger Type
Positive, Negative
Current - Output High, Low
8mA, 8mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74VHCT74AMTCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
©2008 Fairchild Semiconductor Corporation
74VHCT74A Rev. 1.4.0
74VHCT74A
Dual D-Type Flip-Flop with Preset and Clear
Features
n
n
n
n
n
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74VHCT74AM
74VHCT74ASJ
74VHCT74AMTC
High speed: f
High noise immunity: V
Power down protection is provided on all inputs and
outputs
Low power dissipation: I
Pin and function compatible with 74HCT74
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
MAX
= 160MHz (Typ.) at T
IH
CC
= 2.0V, V
= 2µA (Max.) at T
Package
Number
MTC14
M14D
M14A
IL
= 0.8V
A
= 25°C
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
A
= 25°C
General Description
The VHCT74A is an advanced high speed CMOS Dual
D-Type Flip-Flop fabricated with silicon gate CMOS tech-
nology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The signal level applied to
the D INPUT is transferred to the Q OUTPUT during the
positive going transition of the CK pulse. CLR and PR
are independent of the CK and are accomplished by set-
ting the appropriate input LOW.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with V
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V
to 5V systems and two supply systems such as battery
backup.
Package Description
CC
= 0V. These circuits prevent
www.fairchildsemi.com
May 2008

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74VHCT74AMTCX Summary of contents

Page 1

... Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 General Description = 25°C The VHCT74A is an advanced high speed CMOS Dual ...

Page 2

... Connection Diagram Pin Description Pin Names Description Data Inputs Clock Pulse Inputs 1 2 CLR , CLR Direct Clear Inputs Direct Preset Inputs Outputs ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 Logic Symbol IEEE/IEC Truth Table Inputs Outputs CLR Function H Clear L Preset Change n www ...

Page 3

... OUT = 0V < GND, V > (Outputs Active). OUT OUT CC 4. Unused inputs must be held HIGH or LOW. They may not float. ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 Parameter (3) (4) Parameter 3 Rating –0.5V to +7.0V –0.5V to +7.0V –0. 0.5V CC – ...

Page 4

... defined as the value of internal equivalent capacitance which is calculated from the operating PD current consumption without load. Average operating current can be obtained by the equation: (Opr • V • ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4.0 V (V) Conditions CC 4.5 5.5 4.5 5 –50µA 4 ...

Page 5

... Minimum Pulse Width (CK (L) Minimum Pulse Width (CLR, PR Minimum Setup Time S t Minimum Hold Time H t Minimum Removal Time (CLR, PR) REM ©2008 Fairchild Semiconductor Corporation 74VHCT74A Rev. 1.4 25° Guaranteed V (V) Typ. Minimum CC 5.0 ± 0.5 5.0 5.0 ± 0.5 5.0 5.0 ± ...

Page 6

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...

Page 8

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...

Page 9

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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