ds2188st-r Maxim Integrated Products, Inc., ds2188st-r Datasheet

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ds2188st-r

Manufacturer Part Number
ds2188st-r
Description
Ds2188 T1/cept Jitter Attenuator
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
FEATURES
DESCRIPTION
The DS2188 T1/CEPT Jitter Attenuator Chip contains a 128 X 2-bit buffer which, in conjunction with an
external 4X crystal, is used to attenuate the incoming jitter present in clock and data. The device meets all
of the latest applicable specifications including those outlined in TR 62411 (Accunet* T1.5 Service
Description and Interface Specifications, December 1990), TR-TSY-000170 (Digital Cross-Connect
System Requirements and Objectives, November 1985), and the CCITT Recommendations G.735 and
G.742. The DS2188 is compatible with the DS2180A T1/ISDN Primary Rate Transceiver and DS2181A
CEPT Transceiver and is the companion to the DS2187 T1/CEPT Receive Line Interface and DS2186
T1/CEPT Transmit Line Interface. It can also be used in conjunction with the DS2190 T1 Network
Interface Unit.
OVERVIEW
The RCLK input is fed to a 128 x 2-bit FIFO where it drives the write pointer for the positive (RPOS) and
negative (RNEG) data. The read pointer of the FIFO and RRCLK is generated by dividing the frequency
of the crystal connected to XTAL1 and XTAL2 by four. The frequency of the crystal is adjusted by a
DPLL to the long-term average frequency of RCLK. As long as the jitter present at RCLK is less than
120 unit intervals peak-to-peak (UIpp), then the FIFO buffer will be able to absorb the incoming jitter and
it will be attenuated in accordance with TR 62411 (December 1990). In this situation, the BL (Buffer
Limit) pin will remain low. Figures 1 and 2 illustrate the DS2188 Jitter Attenuator performance.
If the incoming jitter has excursions greater than 120 UIpp, then the crystal is adjusted to track the short-
term frequency variations of the incoming signal so that there is no loss of data. This adjustment is
accomplished by dividing the 4X crystal by either 3 ½ or 4 ½ instead of 4. When the incoming jitter is
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Attenuates clock and data jitter present in T1
or CEPT lines
Meets
outlined in TR62411, TR-TSY-000170,
G.735, and G.742
Only one external component required; either
a 6.176 MHz (T1) or 8.192 MHz (CEPT)
crystal
Selectable buffer size of 128 or 32 bits
Jitter attenuation is easily disabled
Single +5V supply; low-power CMOS
technology
Available in 16-pin DIP and 16-pin SOIC
(DS2188S)
Companion to the DS2186 Transmit Line
and DS2187 Receive Line Interface
the
jitter
attenuation
templates
1 of 10
PIN ASSIGNMENT
ORDERING INFORMATION
DS2188
DS2188S
DS2188N
DS2188SN
XTAL OUT
T1/CEPT Jitter Attenuator
RPOS
RNEG
RCLK
TEST
BDS
DJA
VSS
1
3
5
2
4
6
7
8
16 Pin dip
16 Pin SOIC (0º-+70ºC)
16 Pin dip
16 Pin SOIC (-40ºC-+85-ºC)
16
15
14
13
12
11
10
9
(0ºC-F70ºC)
(-40ºC-+85ºC)
VDD
RRPOS
RRNEG
RRCLK
RST
BL
XTAL2
XTAL1
DS2188
100600

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ds2188st-r Summary of contents

Page 1

FEATURES Attenuates clock and data jitter present CEPT lines Meets the jitter attenuation outlined in TR62411, TR-TSY-000170, G.735, and G.742 Only one external component required; either a 6.176 MHz (T1) or 8.192 MHz (CEPT) crystal Selectable ...

Page 2

UIpp, the BL pin will transition high. When the incoming jitter returns to less than 120 UIpp, the BL pin will return low. The jitter attenuator in the DS2188 can be disabled by tying the DJA pin ...

Page 3

DS2188 CEPT JITTER ATTENUATION PERFORMANCE Figure 2 DS2188 IN THE RECEIVE PATH Figure 3 DS2188 IN THE TRANSMIT PATH Figure DS2188 ...

Page 4

PIN DESCRIPTION Table 1 PIN SYMBOL TYPE DESCRIPTION 1 DJA I 2 RPOS I 3 RNEG I 4 RCLK I 5 BDS I 6 TEST I 7 XTAL O OUT XTAL1 I 10 XTAL2 O ...

Page 5

CRYSTAL SELECTION GUIDELINES FOR THE DS2188 PARAMETER Parallel resonant frequency Mode Load capacitance Tolerance Pullability Effective series resistance Crystal cut SPECIFICATION 6.176 MHz (T1) or 8.192 MHz (CEPT) Fundamental (16 pF preferred) ±50 ppm over 0 ...

Page 6

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the ...

Page 7

AC ELECTRICAL CHARACTERISTICS PARAMETER RCLK Period RCLK Pulse Width RCLK Rise and Fall Times RPOS, RNEG Setup to RCLK RPOS, RNEG Hold for RCLK Propagation delay from RRCLK to RPOS, RRNEG Valid Propagation delay from XTAL OUT to RRCLK Pulse ...

Page 8

AC TIMING DIAGRAM Figure 5 NOTE: 1. The phase relationship between XTAL OUT and RRCLK can be of either form DS2188 ...

Page 9

DS1288 T1/CEPT JITTER ATTENTUATOR 16-PIN DIP PKG 16-PIN DIM MIN MAX AIN 0.740 0.780 MM 18.80 19. 0.240 0.260 MM 6.10 6. 0.120 0.140 MM 3.05 3. 0.300 0.325 MM 7.62 8. ...

Page 10

DS1288S T1/CEPT JITTER ATTENTUATOR 16-PIN SOIC PKG 16-PIN DIM MIN MAX AIN 0.402 0.412 MM 10.21 10. 0.290 0.300 MM 7.37 7. 0.089 0.095 MM 2.26 2. 0.004 0.012 MM 0.102 0. ...

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