ds1863 Maxim Integrated Products, Inc., ds1863 Datasheet - Page 13

• Manufacturer Part Number: ds1863
• Description: Ds1863 Burst-mode Pon Controller With Integrated Monitoring
• Manufacturer: Maxim Integrated Products, Inc.

FETG output is always latched in case it is triggered by
an unmasked alarm condition. Its output polarity is pro-
grammable to allow an external N or P MOSFET to open
during alarms to shut off the laser diode current. If the
FETG output triggers indicating the DS1863 is in shut-
down, then it requires TX-D, soft TX-D, or cycling power
to be reset. Under all conditions when the analog outputs
are re-initialized after being disabled, all the alarms with
the exception of the V
The V
put from attempting to operate when inadequate V
exists to operate the laser driver. Once adequate V
present to clear the V
enabled following the same sequence as power up.
As mentioned before the FETG is an output used to dis-
able the laser current via a series N or P MOSFET. This
requires that the FETG output is capable of sinking or
sourcing current. Because the DS1863 will not know if it
should sink or source current before V
V
high impedance when V
Voltage Operation” section for details and diagram).
The application circuit must use a pull-up or pull-down
resistor on this pin that pulls FETG to the alarm/shut-
down state (high for a PMOS, low for a NMOS). Once
V
put to the state determined by the FETG DIR bit (Table
02h, Register 89h). FETG DIR will be 0 if an NMOS is
used and 1 if a PMOS is used.
Figure 5. DS1863 TX-F Timing.
POA
CC
is above V
, which triggers the EE recall, this output will be
CC
low alarm must remain active to prevent the out-
POA
, the DS1863 will pull the FETG out-
CC
CC
low ADC alarm will be cleared.
CC
low alarm, the outputs will be
is below V
DETECTION OF
DETECTION OF
TX-F RESET
TX-F FAULT
TX-F FAULT
TX-D OR
TX-F LATCHED OPERATION
TX-F NON-LATCHED OPERATION
TX-F
TX-F
____________________________________________________________________
POA
CC
. (see “Low
exceeds
CC
Burst-Mode PON Controller
With Integrated Monitoring
CC
is
To determine the cause of the TX-F or FETG alarm, the
system processor can read the DS1863’s Alarm Trap
Bytes (ATB) through the I
ATB have a bit for each alarm. Any time an alarm occurs,
regardless of the mask bit’s state, the DS1863 sets the
corresponding bit in the ATB. Active ATB bits will remain
set until written to zeros via the I
up the ATB will be zeros until alarms dictate otherwise.
DS1863 will have an ID hard coded to its die. Two reg-
isters (Table 02h bytes 86h–87h) are assigned for this
feature. Byte 86h will read 63h to identify the part as the
DS1863, byte 87h will read to A1h (for A1 die revision).
The DS1863 contains two Power-On Reset (POR) lev-
els. The lower level is a Digital POR (V
FETG and MOD and BIAS Outputs as a
Function of TX-D and Alarm Sources
V
V
Yes
Yes
Yes
CC
POA
>
TX-D
0
0
1
NON-MASKED
FETG ALARM
Determining Alarm Causes
X
0
1
2
Using The I
C interface (in Table 01h). The
Low-Voltage Operation
2
FETG DIR
FETG DIR
FETG DIR
Die Identification
C interface. On power
FETG
2
C Interface
POD
MOD AND
OUTPUTS
Disabled
Disabled
Enabled
) and the
BIAS
13