upd16879 Renesas Electronics Corporation., upd16879 Datasheet - Page 25

• Manufacturer Part Number: upd16879
• Description: Monolithic Quad H Bridge Driver Circuit
• Manufacturer: Renesas Electronics Corporation.

About Power Save Mode
Circuit consumption current in the PS mode becomes 300 A (MAX.) at the time of the outside clock (OSC
MHz, and becomes 100 A (MAX.) at the time of the outside clock (OSC
1/10 in normal mode.
(How to be within PS mode)
(Effective timing of PS mode)
(PS mode release movement)
It is possible that circuit electric current is made small in the power saving (the following PS) mode.
Data maintenance just before the PS mode and the maintenance of the phase position are done in the PS mode.
The establishment of the PS mode is done by a D7 bits of the 4th byte.
Please follow the following process when it is within PS mode.
(1)
(2-1) Normal operation (Pulse number = 0, enable: conducts)
(2-2) Normal operation (Pulse number = 0, enable: stops)
(3)
Chopping movement stops at the LATCH falling timing which PS data are contained to.
First point wait count and first point magnetize wait count stop at the next V
contained to. FF1 is fixed on the high level, and FF2 is fixed on low level.
Enable becomes low level at the LATCH falling timing which PS data are contained to.
And, the outside expansion circuit (EXP terminal) works at the time of PS mode too.
Chopping movement resumes at the LATCH falling timing which PS release data are contained to.
First point wait count and first point magnetize wait count resume at the next V
data are contained to.
Enalbe becomes high level at the first FF1 falling timing which PS release data are contained to. (When enable
data is high level)
Normal operation (Pulse number > 1, enable: conducts)
Please input PS data.
Data Sheet S14188EJ1V0DS00
IN
) stopped. It can be reduced in less than
D
D
rising timing which PS data are
rising timing which PS release
PD16879
IN
) = 4.5
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