upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 215

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Address: FF98H
Symbol
WDTM
Notes 1.
Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM
Remarks 1. f
WDCS4
WDCS2
7
0
0
0
1
0
0
0
0
1
1
1
1
Note 1
Note 2
2.
After reset: 67H
2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “internal oscillator cannot be
3. After reset is released, WDTM can be written only once by an 8-bit memory
4. WDTM cannot be set by a 1-bit memory manipulation instruction.
5. If “internal oscillator can be stopped by software” is selected by the option byte and
2. f
3.
4. Figures in parentheses apply to operation at f
WDCS3
WDCS1
If “internal oscillator cannot be stopped” is specified by the option byte, this cannot be set.
The internal oscillation clock will be selected no matter what value is written.
Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Figure 10-2. Format of Watchdog Timer Mode Register (WDTM)
R
XP
when the CPU is operating on the subsystem clock and the high-speed system clock
is stopped. For details, see CHAPTER 29 CAUTIONS FOR WAIT.
stopped” is selected by the option byte, other values are ignored).
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated. If the source clock to the watchdog timer is stopped, however,
an internal reset signal is generated when the source clock to the watchdog timer
resumes operation.
the watchdog timer is stopped by setting WDCS4 to 1, the watchdog timer does not
resume operation even if WDCS4 is cleared to 0. In addition, the internal reset signal
is not generated.
: Don’t care
: Internal oscillation clock oscillation frequency
: High-speed system clock oscillation frequency
6
1
0
1
0
0
1
1
0
0
1
1
Note 1
Note 2
WDCS0
Internal oscillation clock (f
High-speed system clock (f
Watchdog timer operation stopped
R/W
0
1
0
1
0
1
0
1
5
1
CHAPTER 10 WATCHDOG TIMER
Note 2
User’s Manual U16961EJ4V0UD
During internal oscillation clock
2
2
2
2
2
2
2
2
11
12
13
14
15
16
17
18
WDCS4
/f
/f
/f
/f
/f
/f
/f
/f
R
R
R
R
R
R
R
R
4
(4.27 ms)
(8.53 ms)
(17.07 ms)
(34.13 ms)
(68.27 ms)
(136.53 ms)
(273.07 ms)
(546.13 ms)
operation
Operation clock selection
R
)
XP
WDCS3
)
3
Overflow time setting
R
WDCS2
= 480 kHz (MAX.), f
2
During high-speed system clock
2
2
2
2
2
2
2
2
13
14
15
16
17
18
19
20
/f
/f
/f
/f
/f
/f
/f
/f
XP
XP
XP
XP
XP
XP
XP
XP
(819.2 s)
(1.64 ms)
(3.28 ms)
(6.55 ms)
(13.11 ms)
(26.21 ms)
(52.43 ms)
(104.86 ms)
WDCS1
operation
1
XP
WDCS0
= 10 MHz
0
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