upd78f0103hmca1-5a4-a Renesas Electronics Corporation., upd78f0103hmca1-5a4-a Datasheet - Page 179

• Manufacturer Part Number: upd78f0103hmca1-5a4-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(3) When the CPU clock is the internal oscillation clock (f
CPU operation
high-speed system clock (f
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started
using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds
its value.
<1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses.
<2> The CPU clock is switched to the high-speed system clock (f
<1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time
<2> Timing when counting is started after the CPU clock is switched to the high-speed system clock (f
CPU operation
Note Confirm the oscillation stabilization time of f
Watchdog timer
Watchdog timer
select register (OSTS) has elapsed
(CPU Clock: Internal Oscillation Clock, WDT Operation Clock: High-Speed System Clock)
(OSTC).
Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is
selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be switched
without reading the OSTC value.
f
f
XP
XP
(internal oscillation
f
f
(internal oscillation
R
Normal operation
R
Normal operation
Operating
Operating
clock)
clock)
Normal operation (internal oscillation clock)
XP
) when the STOP instruction is executed
Oscillation
Oscillation
stopped
stopped
STOP
STOP
Figure 9-6. Operation in STOP Mode
CHAPTER 9 WATCHDOG TIMER
User’s Manual U16846EJ3V0UD
Operation stopped
Operation stopped
Oscillation stabilization time
Clock supply stopped
Oscillation stabilization time
(set by OSTS register)
Clock supply
17 clocks
XP
(set by OSTS register)
17 clocks
stopped
using the oscillation stabilization time counter status register
R
) and the watchdog timer operation clock is the
XP
).
Normal operation (internal oscillation clock)
CPU clock
f
R
→ f
XP
Note
(high-speed system clock)
Normal operation
Operating
Operating
XP
)
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