upd78f0134hgka1-9et-a Renesas Electronics Corporation., upd78f0134hgka1-9et-a Datasheet - Page 145

• Manufacturer Part Number: upd78f0134hgka1-9et-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Address FFB6H
Symbol
TMC01
TMC013 TMC012 TMC011
OVF01
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF01 flag.
Remark TO01:
0
0
0
0
1
1
1
1
0
1
7
0
Overflow not detected
Overflow detected
0
0
1
1
0
0
1
1
TI001:
TM01:
CR001: 16-bit timer capture/compare register 001
CR011: 16-bit timer capture/compare register 011
2. Set the valid edge of the TI001/P05 pin using prescaler mode register 01 (PRM01).
3. If any the following modes: the mode in which clear & start occurs on match between TM01
6
0
and CR001, the mode in which clear & start occurs at the TI001 pin valid edge, or free-running
mode is selected, when the set value of CR001 is FFFFH and the TM01 value changes from
FFFFH to 0000H, the OVF01 flag is set to 1.
After reset: 00H
Figure 6-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01)
0
1
0
1
0
1
0
1
16-bit timer/event counter 01 output pin
16-bit timer/event counter 01 input pin
16-bit timer counter 01
5
0
Operation stop
(TM01 cleared to 0)
Free-running mode
Clear & start occurs on TI001
pin valid edge
Clear & start occurs on match
between TM01 and CR001
4
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Operating mode and clear
TMC013
R/W
mode selection
3
TMC012
16-bit timer counter 01 (TM01) overflow detection
2
User’s Manual U16899EJ3V0UD
TMC011
1
OVF01
<0>
No change
Match between TM01 and
CR001 or match between
TM01 and CR011
Match between TM01 and
CR001, match between TM01
and CR011 or TI001 pin valid
edge
Match between TM01 and
CR001 or match between
TM01 and CR011
Match between TM01 and
CR001, match between TM01
and CR011 or TI001 pin valid
edge
TO01 inversion timing selection
Not generated
<When used as compare
register>
Generated on match between
TM01 and CR001, or match
between TM01 and CR011
<When used as capture
register>
Generated by inputting CR001
capture trigger
Interrupt request generation
145