si5018 Silicon Laboratories, si5018 Datasheet
si5018
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si5018 Summary of contents
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... PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5018 represents a new standard in low jitter, low power, and small size for high speed CDRs. It operates from a single 2.5 V supply over the industrial temperature range (– °C). ...
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... Si5018 2 Rev. 1.3 ...
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... Forward Error Correction (FEC Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Descriptions: Si5018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Rev. 1.3 ...
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... Si5018 1. Detailed Block Diagram DIN+ DIN+ Phase Phase Phase Detector Detector Detector DIN– REFCLK+ REFCLK+ REFCLK– REXT Bias Bias Bias G eneration G eneration G eneration 4 CLK A/D VCO DSP Divider n Lock Detector Calibration Rev. 1.3 DOUT+ Retim e Retim e Retim e DOUT– c CLKOUT+ c CLKOUT– ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5018 specifications are guaranteed when using the recommended application circuit (including component tolerance) shown in "Typical Application Schematic‚" on page 9. ...
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... Si5018 Table 2. DC Characteristics (V = 2.5 V ±5 – ° Parameter Supply Current Power Dissipation Common Mode Input Voltage (DIN, REFCLK)* Single Ended Input Voltage (DIN, REFCLK)* Differential Input Voltage Swing (DIN, REFCLK)* Input Impedance (DIN, REFCLK) Differential Output Voltage Swing (DOUT) ...
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... GEN(rms) J with no jitter on serial data GEN(PP After falling edge of AQ PWRDN/CAL From the return of valid data C DUTY C TOL LOL LOCK Rev. 1.3 Si5018 Min Typ Max Unit 2.4 — 2.7 GHz — 80 110 ps 225 250 270 ps 225 250 270 — ...
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... Si5018 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
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... Typical Application Schematic DIN+ High-Speed Serial Input DIN– System REFCLK+ Reference REFCLK– Clock Powerdown Loss-of-Lock Indicator DOUT+ DOUT– Si5018 CLKOUT+ CLKOUT– 0.1 μF 10 kΩ VDD (1%) 2200 Rev. 1.3 Si5018 Recovered Data Recovered Clock 9 ...
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... REFCLK, indicating the lock status of the PLL is unknown. Additionally, the Si5018 uses the reference clock to center the VCO output frequency at the OC-48/STM-16 data rate. The device will self- configure for operation with one of three reference clock frequencies ...
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... When PWRDN/CAL is released (set to low) the digital logic resets to a known initial condition, recalibrates the DSPLL, and will begin to lock to the data stream. 4.8. Device Grounding The Si5018 uses the GND pad on the bottom of the 20- Rev. 1.3 Si5018 20 dB/Decade Slope f0 ...
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... See Figures 10 and 11 for the ground (GND) pad location. 4.9. Bias Generation Circuitry The Si5018 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces ...
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... Clock source 0.1 μ Ω Figure 8. Single-Ended Input Termination for DIN (AC Coupled) Si5018 VDD 2.5 kΩ DIN + 10 kΩ 2.5 kΩ 102 Ω 100 Ω DIN – 10 kΩ 0.1 μF GND Rev. 1.3 Si5018 13 ...
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... Si5018 4.11. Differential Output Circuitry The Si5018 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc coupling is possible, the 0.1 μF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6 ...
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... VDD Figure 10. Si5018 Pin Configuration Table 8. Si5018 Pin Descriptions I/O Signal Level External Bias Resistor. This resistor is used by onboard circuitry to estab- lish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resis- tor. Differential Reference Clock. ...
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... Si5018 Table 8. Si5018 Pin Descriptions (Continued) Pin # Pin Name 15 PWRDN/CAL 16 CLKOUT– 17 CLKOUT 11, 14 VDD 3, 8, 18, 19, GND 20, and GND Pad 16 I/O Signal Level I LVTTL Powerdown. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low ...
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... These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being fully compatible with both leaded and lead-free card assembly processes. 7. Top Mark Silicon Labs Part Number Si5018-B-GM Voltage Pb-Free 2.5 Yes Die Revision (R) Assembly Date (YWW Last digit of current year WW = Work week Rev. 1.3 Si5018 Temperature – °C 17 ...
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... Si5018 8. Package Outline Figure 11 illustrates the package details for the Si5018. Table 9 lists the values for the dimensions shown in the illustration. Figure 11. 20-pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 c — — D 4.00 BSC D2 1.95 2.10 e 0.50 BSC E 4.00 BSC Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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... A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended not place any signal or power plane vias in these “keep out” regions. 9. Suggest four 0.38 mm (15 mil) vias to the ground plane. See Note 9 Gnd Pin Parameter Min 2.23 2.03 2.43 0.23 4.26 Rev. 1.3 Si5018 Dimensions Nom Max 2.25 2.28 2.08 2.13 — 0.50 BSC — 2.46 2.48 — ...
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... Si5018 OCUMENT HANGE IST Revision 1.0 to Revision 1.1 Added "Top Mark‚" on page 17. Updated "Package Outline‚" on page 18. Added "4x4 mm 20L QFN Recommended PCB Layout‚" on page 19. Revision 1.1 to Revision 1.2 Made minor note corrections to "4x4 mm 20L QFN Recommended PCB Layout‚" on page 19. ...
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... N : OTES Rev. 1.3 Si5018 21 ...
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... Si5018 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 7801 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...