si5540 Silicon Laboratories, si5540 Datasheet
si5540
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si5540 Summary of contents
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... Support for data streams up to 10.7 Gbps is also provided for applications that employ forward error correction (FEC). The Si5540 represents a new standard in low jitter, low power and small size for 10 Gbps serial transmitters. It operates from a single 1.8 V supply over the industrial temperature range (– C). ...
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Si 5540 2 Preliminary Rev. 0.31 ...
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... Section Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DSPLL™ Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Si5540 Pinout: 99-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin Descriptions: Si5540 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Preliminary Rev. 0.31 Si5540 Page 3 ...
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... Table 1. Recommended Operating Conditions Parameter Ambient Temperature LVTTL Output Supply Voltage Si5540 Supply Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature unless otherwise stated. V ...
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... IL V ISE V ICM V 100 Load OH Line-to-Line V 100 Load OL Line-to-Line V 100 Load OSE Line-to-Line, See Figure 1 V OCM I SC– I SC+ V IL2 Preliminary Rev. 0.31 Si5540 Min Typ Max Unit — 333 TBD mA — 0.6 TBD W .8 0.9 1.0 V 800 1000 1200 mV (pk-pk) 1.975 2.3 2.59 V 1.32 1.6 1.99 V 250 — ...
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Si 5540 Table 2. DC Characteristics 1.8 V ±5 –40°C to 85° Parameter Input Voltage High (TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, REFRATE, REFSEL, TXMSBSEL, RESET) Input Low Current (TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, REFRATE, ...
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... R F Symbol Test Condition J PRBS-23 DET(PP) J GEN(RMS) J BWSEL = 0 BW BWSEL = 1 T Valid REFCLK AQ RC REFRATE = 1 FREQ REFRATE = 0 RC DUTY RC TOL Preliminary Rev. 0.31 Si5540 Min Typ Max Unit — 9.95 10.7 GHz 45 — — 25 — ps — 25 — — — — — ...
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Si 5540 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range Package Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k ...
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... The selection of reference clock configuration is controlled via the REFSEL input. The Si5540 will drive the TXLOL output high to indicate the DSPLL has locked to the selected reference source. ...
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... Bias Generation Circuitry The Si5540 makes use of an external resistor to set internal bias currents. The external resistor allows pre- cise generation of bias currents which significantly reduces power consumption versus traditional imple- mentations that use an internal resistor ...
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... Differential Output Circuitry The Si5540 utilizes a current-mode logic (CML) architecture to drive the high speed serial output clock and data on TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 4. In applications where direct dc coupling is possible, the 250 nF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 5 ...
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... GND TXDIN[6]+ GND TXDIN[7]+ TXDIN[6]– TXDIN[7]– GND TXDIN[4]+ TXDIN[5]+ GND TXDIN[4]– TXDIN[3]+ TXDIN[5]– TXDIN[2]+ TXDIN[2]– TXDIN[0]+ Figure 5. Si5540 Pin Configuration (Bottom View TXDIN[14]+ REFCLK– REFCLK+ TXSQLCH TXDIN[13]+ TXDIN[15]– TXDIN[15]+ TXCLKDSBL GND GND ...
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... RSVD_ G TXDOUT– GND GND H GND NC BWSEL RSVD_ J REXT TXLOL GND TXCLK16 K FIFOERR FIFORST OUT– Figure 6. Si5540 Pin Configuration (Transparent Top View TXSQLCH REFCLK+ REFCLK- TXDIN[14]+ TXCLKDSBL TXDIN[15]+ TXDIN[15]– TXDIN[13]+ RESET GND GND GND VDD VDD VDD ...
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... Differential Reference Clock. I LVPECL The reference clock sets the operating fre- quency of the PLL used to generate the output clock frequency. The Si5540 will operate with reference clock frequencies that are either 1/ 16th or 1/64th the output clock rate. Reference Frequency Select. I LVTTL ...
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... This clock output is generated by dividing down the high speed output clock, TXCLKOUT factor of 16 intended for use in counter clocking schemes that transfer data between the system ASIC and the Si5540. High Speed Clock Disable. I LVTTL When this input is high, the output driver for TXCLKOUT is disabled ...
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Si 5540 Pin Number(s) Pin Name J4 TXMSBSEL A4 TXSQLCH D4–7, E4–7, VDD F4–7, G4–7, C3 VDD33 16 I/O Signal Level Data Bus Transmit Order. I LVTTL For TXMSBSEL = 0, data on TXDIN[0] is trans- mitted first followed by ...
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... Ordering Guide Part Number Si5540-BC Table 7. Ordering Guide Package Temperature 99 BGA –40° 85° C Preliminary Rev. 0.31 Si5540 17 ...
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... Si 5540 Package Outline Figure 7 illustrates the package details for the Si5540. Table 8 lists the values for the dimensions shown in the illustration. A1 Ball Pad Corner D Top View Table 8. Package Diagram Dimensions Seating Plane Side View Figure 7. 99-Ball Grid Array (BGA) ...
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... Preliminary Rev. 0.31 Si5540 19 ...
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... Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages ...