si5367 Silicon Laboratories, si5367 Datasheet
si5367
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si5367 Summary of contents
Page 1
... VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5367 is ideal for providing clock multiplication in high performance timing applications. Applications SONET/SDH OC-48/OC-192 STM-16/STM-64 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G ...
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... Si5367 Table 1. Performance Specifications (V = 1.8 ±5% or 2.5 V ±10 – º Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, CKIN2, CKIN3, CKIN4) Output Clock Frequency CK OF (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5) 3-Level Input Pins ...
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... MHz offset Phase Noise @ 100 kHz Offset Max spur @ > < 100 MHz) Still Air www.silabs.com/timing Symbol DIG T JCT T STG Preliminary Rev. 0.4 Si5367 Min Typ Max Unit –40 — — 0.6 TBD ps rms — 0.6 TBD ps rms — ...
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... Si5367 622 MHz In, 622 MHz Out BW=877 kHz -50 -70 -90 -110 -130 -150 -170 1000 10000 OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to 80 MHz Broadband, 800 MHz 4 100000 1000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot ...
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... CKIN4+ CKIN4– 82 Ω 82 Ω Control Mode (H) CMODE RST Reset *Note: Assumes differential LVPECL termination (3 clock inputs. Figure 3. Si5367 Typical Application Circuit (SPI Control Mode Ferrite 1 µF Bead C 1–9 0.1 µF CKOUT1+ CKOUT1– CKOUT5+ CKOUT5– ...
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... Si5367 1. Functional Description The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 10 to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range ...
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... Table 3. Si5367 Pin Descriptions I/O Signal Level No Connect. These pins must be left unconnected for normal opera- tion. I LVCMOS External Reset. Active low input that performs external hardware reset of device. Resets all internal logic to a known state and forces the device registers to their default value ...
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... Si5367 Table 3. Si5367 Pin Descriptions (Continued) Pin # Pin Name 5, 6, 15, 27, 32 42, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99, 100 7, 8, 14, 16, 18, GND 19, 21, 26, 28, 31, 33, 36, 38, 41, 43, 46, 54, 55, 64 C1B 10 C2B 11 C3B Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. ...
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... Table 3. Si5367 Pin Descriptions (Continued) Pin # Pin Name 12 INT_ALM 13 CS0_C3A 57 CS1_C4A 29 CKIN4+ 30 CKIN4– 34 CKIN2+ 35 CKIN2– Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. I/O Signal Level O LVCMOS Interrupt/Alarm Output Indicator. This pin functions as a maskable interrupt output with active polarity controlled by the INT_POL register bit ...
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... Si5367 Table 3. Si5367 Pin Descriptions (Continued) Pin # Pin Name 39 CKIN3+ 40 CKIN3– 44 CKIN1+ 45 CKIN1– 58 C1A 59 C2A 60 SCL 61 SDA_SDO A2_SS Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. 10 I/O Signal Level I MULTI Clock Input 3. Differential clock input. This input can also be driven with a single-ended signal ...
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... Table 3. Si5367 Pin Descriptions (Continued) Pin # Pin Name 71 SDI 77 CKOUT3+ 78 CKOUT3– 82 CKOUT1– 83 CKOUT1+ 87 CKOUT5– 88 CKOUT5+ 90 CMODE 92 CKOUT2+ 93 CKOUT2– 97 CKOUT4– 98 CKOUT4+ GND PAD GND PAD Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map. ...
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... Ordering Guide Ordering Part Output Clock Number Frequency Range Si5367A-C-GQ 10–945 MHz 970–1134 MHz 1.213–1.417 GHz Si5367B-C-GQ 10–808 MHz Si5367C-C-GQ 10–346 MHz 12 Package ROHS6, Pb-Free 100-Pin TQFP Yes 100-Pin TQFP Yes 100-Pin TQFP Yes Preliminary Rev ...
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... Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Package Diagram Dimensions 100-Pin Max Dimension — 1.20 E — 0.15 E1 1.05 E2 0.27 L — 0.20 aaa bbb ccc 4.15 ddd θ Preliminary Rev. 0.4 Si5367 Min Nom Max 16.00 BSC 14.00 BSC 3.85 4.00 4.15 0.45 0.60 0.75 — — 0.20 — — 0.20 — — 0.08 — — 0.08 0º ...
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... Si5367 5. Recommended PCB Layout 14 Figure 5. PCB Land Pattern Diagram Preliminary Rev. 0.4 ...
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... Notes (Card Assembly No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.4 MIN MAX 0.50 BSC. 15.40 REF. 15.40 REF. 3.90 4.10 3.90 4.10 13.90 — 13.90 — — 0.30 1.50 REF. — 16.90 — 16.90 0.15 REF — 1.00 Si5367 15 ...
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... Updated “2. Pin Descriptions: Si5367”. Changed font of register names to underlined italics. Updated "3. Ordering Guide" on page 12. Added “5. Recommended PCB Layout”. Revision 0.3 to Revision 0.5 Changed 1.8 V operating range to ±5%. Clarified "2. Pin Descriptions: Si5367" on page 7. Updated "4. Package Outline: 100-Pin TQFP" on page 13. 16 Preliminary Rev. 0.4 ...
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... N : OTES Preliminary Rev. 0.4 Si5367 17 ...
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... Si5367 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...