si5367 Silicon Laboratories, si5367 Datasheet - Page 6

• Manufacturer Part Number: si5367
• Description: ?p-programmable Precision Clock Multiplier
• Manufacturer: Silicon Laboratories

Si5367
1. Functional Description
The Si5367 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs
ranging from 10 to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 10 to
945 MHz and select frequencies to 1.4 GHz. The device
provides virtually any frequency translation combination
across this operating range. Independent dividers are
available for every input clock and output clock, so the
Si5367 can accept input clocks at different frequencies
and it can generate output clocks at different
frequencies. The Si5367 input clock frequency and
clock multiplication ratio are programmable through an
I
based software utility, DSPLLsim, that can be used to
determine the optimum PLL divider settings for a given
input frequency/clock multiplication ratio combination
that minimizes phase noise and power consumption.
This
http://www.silabs.com/timing
The Si5367 is based on Silicon Laboratories' 3rd-
generation DSPLL
rate frequency synthesis in a highly integrated PLL
solution that eliminates the need for external VCXO and
loop filter components. The Si5367 PLL loop bandwidth
is digitally programmable and supports a range from
30 kHz to 1.3 MHz. The DSPLLsim software utility can
be used to calculate valid loop bandwidth settings for a
given input clock frequency/clock multiplication ratio.
The Si5367 monitors all input clocks for loss-of-signal
and provides a LOS alarm when it detects missing
pulses on its inputs.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5367 has five differential clock outputs. The
signal format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. In addition, the phase of
each output clock may be adjusted in relation to the
other output clocks. The resolution varies from 800 ps to
2.2 ns depending on the PLL divider settings. Consult
the DSPLLsim configuration software to determine the
phase offset resolution for a given input clock/clock
multiplication
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8
or 2.5 V supply.
6
2
C or SPI interface. Silicon Laboratories offers a PC-
utility
ratio
can
®
technology, which provides any-
combination.
be
(click on Documentation).
downloaded
For
system-level
Preliminary Rev. 0.4
from
1.1. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for detailed
information about the Si5367. Additional design support
is available from Silicon Laboratories through your
distributor.
Silicon Laboratories has developed a PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.