mach120 Lattice Semiconductor Corp., mach120 Datasheet
mach120
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mach120 Summary of contents
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... SpeedLocking™ for guaranteed fixed timing Pin-compatible with the MACH221 GENERAL DESCRIPTION The MACH120 is a member of the high-performance EE CMOS MACH has approximately five times the logic macrocell capability of the popular PALCE22V10 without loss of speed. The MACH120 consists of four PAL The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks ...
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... I/O Cells 12 Macrocells AND Logic Array and Logic Allocator 26 Switch Matrix AND Logic Array and Logic Allocator OE Macrocells 12 I/O Cells 12 I/O –I CLK Block C CLK MACH120-12/15 I – – CLK / CLK / ...
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... PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage 4 PLCC MACH120-12/15 Block D 60 I/O41 I/O40 59 I/O39 58 I/O38 57 56 I/O37 55 I/O36 ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confir m availability of specific valid combinations and to check on newly released combinations. MACH120-12/15 (Com’l) OPERATING CONDITIONS C = Commercial ( +70 C) PACKAGE TYPE ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confir m availability of specific valid JI combinations and to check on newly released combinations. MACH120-18 (Ind) OPERATING CONDITIONS I = Industrial (– +85 C) PACKAGE TYPE J = 68-Pin Plastic Leaded ...
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... I/O cells; the other two control the last six macrocells. The Logic Allocator The logic allocator in the MACH120 takes the 48 logic product terms and allocates them to the 12 macrocells as needed. Each macrocell can be driven product terms. The design software automatically confi ...
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... The I/O Cell The I/O cell in the MACH120 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to six I/O cells. Within each PAL block, two product terms are available for selection by the fi ...
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... Output Enable Output Enable Figure 1. MACH120 PAL Block MACH120-12/15 I/O I/O Cell Output Macro M Cell 0 I/O Cell I/O Output Macro M Cell 1 I/O Cell I/O Output M Macro 2 Cell I/O I/O Cell Output M Macro 3 Cell I/O ...
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... Max OUT (Note 0 Max (Note 3) OUT = MHz CC A (Note 4) and I (or I and I ). OZL IH OZH MACH120-12/15 (Com’ Min Typ Max Unit 2.4 V 0.5 V 2 -10 A -30 -130 mA 85 ...
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... V = 2.0 V OUT -12 Min Max 12 D-type 7 T-type LOW 6 HIGH 6 D-type 66.7 T-type 62.5 D-type 76.9 ) T-type 71.4 CNT 83 MACH120-12/15 (Com’l) Typ Unit -15 Min Max Unit MHz 47.6 MHz 66.6 MHz 55.5 MHz 83.3 MHz ...
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... Max OUT (Note 0 Max (Note 3) OUT MHz (Note and I (or I and I ). OZL IH OZH MACH120-18 (Ind Min Typ Max Unit 2.4 V 0.5 V 2 -10 A -30 -130 ...
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... MHz V = 2.0 V OUT Parameter Description D-type T-type LOW HIGH D-type External Feedback 1/( T-type D-type Internal Feedback (f ) CNT T-type No Feedback 1/( MACH120-18 (Ind) Typ Unit -18 Min Max Unit 13 7 MHz 38 ...
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... Output, LOW IOH (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH II (mA) 20 –2 – –20 –40 –60 –80 –100 Input MACH120-12/15 VOL (V) .8 1.0 VOH (V) 14129J-5 VI (V) 14129J-6 14129 ...
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... The selected “typical” pattern is a 12-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH120-12/ 14129J-7 15 ...
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... Input rise and fall times 2 ns–4 ns typical. 16 Parameter Description Output Combinatorial Output Clock t Registered Output Clock Width MACH120-12/15 Typ PLCC Unit 13 C/W 37 C/W 200 lfpm air 33 C/W 400 lfpm air 30 C/W 600 lfpm air 28 C/W 800 lfpm air 25 C/W V ...
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... Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical. t ARW ARR V T 14129J-11 Asynchronous Reset t APW APR V T 14129J-12 Asynchronous Preset – 14129J-13 Output Disable/Enable MACH120-12/15 17 ...
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... Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State Output Test Point Commercial 300 5 pF MACH120-12/15 KS000010-PAL 14129J-14 R Measured Output Value 2 1.5 V 390 – ...
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... LOGIC MAX ) CO CLK REGISTER t t HIR SIR + 1/( MAXIR SIR MACH120-12/15 external.” MAX internal”. A simple in- MAX + t ). However Usually designated “f no feed- MAX MAX . Because this MAXIR + the sum of the clock HIR is MAXIR ...
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... Min Pattern Data Retention Time DR N Max Reprogramming Cycles INPUT/OUTPUT EQUIVALENT SCHEMATICS Protection 20 Units 10 Years 20 Years 100 Cycles V CC 100 ESD Input 100 k Preload Feedback Circuitry Input I/O MACH120-12/15 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions 1 k 14129J-15 ...
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... Parameter Symbol t Power-Up Reset Time PR t Input or Feedback Setup Time S t Clock Width LOW WL Power Registered Output Clock Parameter Descriptions Power-Up Reset Waveform MACH120-12/15 can rise CC Max Unit 10 s See Switching Characteristics V CC 14129J-16 21 ...