ds31415 Maxim Integrated Products, Inc., ds31415 Datasheet

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ds31415

Manufacturer Part Number
ds31415
Description
Ds31415 3-input, 4-output, Single Dpll Timing Ic With Sub-ps Output Jitter And 1588 Clock
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
The DS31415 is a flexible, high-performance timing IC
for
synthesis applications. On each of its three input clocks
and four output clocks, the device can accept or
generate nearly any frequency between 2kHz and
750MHz.
The input clocks are divided down, fractionally scaled as
needed, and continuously monitored for activity and
frequency accuracy. The best input clock is selected,
manually or automatically, as the reference clock for the
rest of the device. A flexible, high-performance digital
PLL locks to the selected reference and provides
programmable bandwidth, very high resolution holdover
capability, and truly hitless switching between input
clocks. The digital PLL is followed by a clock synthesis
subsystem that has two fully programmable digital
frequency synthesis blocks, a high-speed low-jitter
APLL, and four output clocks, each with its own 32-bit
divider and phase adjustment. The APLL provides
fractional scaling and output jitter less than 1ps RMS.
For telecom systems, the DS31415 has all required
features and functions to serve as a central timing
function or as a line card timing IC.
In addition the DS31415 has an embedded IEEE 1588
clock that can be steered by system software to follow a
time master elsewhere in the system or elsewhere in
the network. This clock has all necessary features to be
the central time clock in a 1588 ordinary clock,
boundary clock or transparent clock.
Frequency Conversion and IEEE1588 Time/Frequency
Telecom Line Cards or Timing Cards with Any Mix of
+Denotes a lead(Pb)-free/RoHS-compliant package.
SPI is a trademark of Motorola, Inc.
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of
any device may be simultaneously available through various sales channels. For information about device errata, go to:
www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or
visit Maxim’s website at www.maxim-ic.com.
19-5712; Rev 1; 3/11
DS31415GN+
Applications in a Wide Variety of Equipment Types
SONET/SDH, Synchronous Ethernet and/or OTN
Ports in WAN Equipment Including MSPPs, Ethernet
Switches, Routers, DSLAMs, and Base Stations
diverse
PART
frequency
-40C to +85C
TEMP RANGE
Ordering Information
with Sub-ps Output Jitter and 1588 Clock
General Description
3-Input, 4-Output, Single DPLL Timing IC
conversion
ABRIDGED DATA SHEET
Applications
and
PIN-PACKAGE
256 CSBGA
frequency
Three Input Clocks
High-Performance DPLL
Two Digital Frequency Synthesizers
High-Performance Output APLL
Four Output Clocks in Two Groups
IEEE 1588 Clock Features
General Features
Differential or CMOS/TTL Format
Any Frequency from 2kHz to 750MHz
Fractional Scaling for 64B/66B and FEC Scaling
(e.g., 64/66, 237/255, 238/255) or Any Other
Downscaling Requirement
Continuous Input Clock Quality Monitoring
Three 2/4/8kHz Frame Sync Inputs
Hitless Reference Switching on Loss of Input
Automatic or Manual Phase Build-Out
Holdover on Loss of All Inputs
Programmable Bandwidth, 0.5mHz to 400Hz
Produce Any 2kHz Multiple Up to 77.76MHz
Per-DFS Phase Adjustment
Output Frequencies to 750MHz
High Resolution Fractional Scaling for FEC and
64B/66B (e.g., 255/237, 255/238, 66/64) or Any
Other Scaling Requirement
Less than 1ps RMS Output Jitter
Nearly Any Frequency from < 1Hz to 750MHz
Each Group Slaves to a DFS Clock, Any APLL
Clock, or Any Input Clock (Divided and Scaled)
Each Has a Differential Output (3 CML, 4 LVDS/
LVPECL
32-Bit Frequency Divider Per Output
Two Sync Pulse Outputs: 8kHz and 2kHz
Steerable by Software with 2
Resolution and 2
4ns Input Timestamp Accuracy and Output
Edge Placement Accuracy
Programmable Clock and Time-Alignment I/O to
Synchronize All 1588 Devices in Large Systems
Supports 1588 OC, BC, and TC Architectures
Suitable Line Card IC or Timing Card IC for
Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU
Accepts and Produces Nearly Any Frequency
from 1Hz Up to 750MHz
Internal Compensation for Local Oscillator Frequency Error
SPI™ Processor Interface
1.8V Operation with 3.3V I/O (5V Tolerant)
)
and Separate CMOS/TTL Output
-32
Maxim Integrated Products 1
ns Frequency Resolution
DS31415
-8
ns Time
Features

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ds31415 Summary of contents

Page 1

... For telecom systems, the DS31415 has all required features and functions to serve as a central timing function line card timing IC. In addition the DS31415 has an embedded IEEE 1588 clock that can be steered by system software to follow a time master elsewhere in the system or elsewhere in the network ...

Page 2

... Typical Application Example, Frequency and Time Synchronization from port cards, for SyncE or 1588+SyncE operation Processor 1588 Software Local OSC TCXO or SPI OCXO DS31415 1588 system time, e.g. 1 PPS Clock line clocks, e.g. 25MHz system clock, e.g. 25MHz DPLL other clocks packet data to/from central switch function to all port cards DS31415 2 ...

Page 3

... HW Control and Status Pins MCLKOSC Local Oscillator TCXO or OCXO 1588 out1 FSYNC 1588 out2 MFSYNC Divider Muxes Dif Mux Divider 1 OC1 APLL1 OC1POS/NEG lowest jitter path OC4 Divider 4 OC4POS/NEG MCLK clkin out1 ICx 1588 OCx Clock out2 SYNCx tain ICx OCx DS31415 3 ...

Page 4

... Simultaneously produce four different output frequencies from the same reference clock  Standard telecom output frequencies include 622.08MHz, 155.52MHz, and 19.44MHz for SONET/SDH and 156.25MHz, 125MHz, and 25MHz for Synchronous Ethernet  Very high-resolution fractional scaling (i.e., noninteger multiplication)  Less than 1ps RMS output jitter DS31415 4 ...

Page 5

... Internal compensation for local oscillator frequency error Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet and click on Request Full Data Sheet. www.maxim-ic.com/DS31415 ) -32 ns frequency resolution DS31415 ≤ 750MHz) and a and a separate ≤ 312.5MHz) 5 ...

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