S25FL064P Meet Spansion Inc., S25FL064P Datasheet
S25FL064P
Available stocks
Related parts for S25FL064P
S25FL064P Summary of contents
Page 1
... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL064P_00 Notice On Data Sheet Designations Revision 02 S25FL064P Cover Sheet for definitions. Issue Date July 2, 2009 ...
Page 2
... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL064P S25FL064P_00_02 July 2, 2009 ...
Page 3
... CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Publication Number S25FL064P_00 This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual- ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications ...
Page 4
... This device requires a high voltage supply to the W#/ACC pin to enable the Accelerated Programming mode. The S25FL064P device also offers a One-Time Programmable area (OTP 128-bits (16 bytes) for permanent secure identification and an additional 490 bytes of OTP space for other use. This OTP area can be programmed or read using the OTPP or OTPR instructions ...
Page 5
... OTP Program (OTPP 9.23 Read OTP Data Bytes (OTPR 10. OTP Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1 Programming OTP Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.2 Reading OTP Data 10.3 Locking OTP Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11. Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12. Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 July 2, 2009 S25FL064P_00_02 S25FL064P 5 ...
Page 6
... SO3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width 19.2 WSON 8-contact ( mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 19.3 FAB024 — 24-ball Ball Grid Array ( mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 20. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL064P S25FL064P_00_02 July 2, 2009 ...
Page 7
... AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 18.1 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 18.2 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 18.3 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 18.4 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = July 2, 2009 S25FL064P_00_02 S25FL064P 7 ...
Page 8
... Table 7.2 Configuration Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 7.3 TBPROT = 0 (Starts Protection from TOP of Array .17 Table 7.4 TBPROT=1 (Starts Protection from BOTTOM of Array .17 Table 8.1 S25FL064P Sector Address Table TBPARM .20 Table 8.2 S25FL064P Sector Address Table TBPARM .21 Table 9.1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Table 9.2 Manufacturer & Device ID - RDID (JEDEC 9Fh .31 Table 9.3 Product Group CFI Query Identification String ...
Page 9
... Block Diagram SRAM Logic July 2, 2009 S25FL064P_00_02 Array - S25FL064P Array - DATA PATH 9 ...
Page 10
... GND 4 SI/IO0 5 Figure 2.3 24-ball SPI BGA ( mm SCK GND VCC C NC CS# NC W#/ACC/IO2 D NC SO/IO1 SI/IO0 HOLD#/IO3 S25FL064P SCK SI/IO0 DNC DNC DNC DNC GND W#/ACC/IO2 S25FL064P_00_02 July 2, 2009 ...
Page 11
... Input CC GND Input 4. Logic Symbol July 2, 2009 S25FL064P_00_02 Description Serial Data Output: Transfers data serially out of the device on the falling edge of SCK. Functions as an input pin in Dual and Quad I/O, and Quad Page Program modes. ...
Page 12
... Device Family S25FL Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL064P Valid Combinations Table S25FL064P Valid Combinations Package & Speed Option Temperature MFI,NFI 0X MFV, NFV BFI S25FL064P Packing Type ...
Page 13
... The Write Protect/Accelerated Programming (W#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. CPOL Mode 0 0 Mode 3 1 July 2, 2009 S25FL064P_00_02 Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SI SCK ...
Page 14
... Write in Progress (WIP) bit in the Status Register. The Read from Status Register command provides the state of the WIP bit. In addition, the S25FL064P device offers two additional bits in the Status Register (P_ERR, E_ERR) to indicate whether a Program or Erase operation was a success or failure. ...
Page 15
... July 2, 2009 S25FL064P_00_02 Table 9.8, S25FL064P Status Register on page Table 7.1 Suggested Cross Settings Parameter Sectors - Bottom 0 1 Not recommended (Parameters & BP Protection are both Bottom) 0 Not recommended (parameters & BP Protection are both Top) ...
Page 16
... Locks BP2-0 bits in the Status Register S25FL064P Description Not Used Not Used 1 = Bottom Array (low address Top Array (high address) (Default) Do Not Use 1 = Volatile 0 = Non-volatile (Default Top Array (high address Bottom Array (low address) (Default Quad I Dual or Serial I/O (Default Enabled 0 = Disabled (Default) S25FL064P_00_02 July 2, 2009 ...
Page 17
... July 2, 2009 S25FL064P_00_02 Table 7.3 TBPROT = 0 (Starts Protection from TOP of Array) Memory Array Protected Address Range Protected Sectors None 0 7E0000h-7FFFFFh (2) SA127:SA126 7C0000h-7FFFFFh (4) SA127:SA124 780000h-7FFFFFh (8) SA127:SA120 700000h-7FFFFFh ...
Page 18
... Note: The HOLD Mode feature is disabled when Quad mode is enabled, i.e., Quad bit in the Configuration register is set to “1”. SCK HOLD 7.1. Figure 7.1 Hold Mode Operation Hold Condition (standard use) S25FL064P Figure 7.1, standard use). If the Hold Condition (non-standard use) S25FL064P_00_02 July 2, 2009 ...
Page 19
... P4E/P8E commands. show the starting and ending address for each sector. The complete set of sectors comprises the memory array of the Flash device. July 2, 2009 S25FL064P_00_02 S25FL064P ...
Page 20
... Table 8.1 S25FL064P Sector Address Table TBPARM=0 Address range Sector Sector Start End address Address SA127 7F0000h 7FFFFFh SA84 SA126 7E0000h 7EFFFFh SA83 SA125 7D0000h 7DFFFFh SA82 SA124 7C0000h 7CFFFFh SA81 SA123 7B0000h 7BFFFFh SA80 SA122 7A0000h 7AFFFFh SA79 SA121 790000h 79FFFFh ...
Page 21
... Table 8.2 S25FL064P Sector Address Table TBPARM=1 Address range Sector Sector Start End address Address SS31 7FF000h 7FFFFFh SA127 SS30 7FE000h 7FEFFFh SA126 SS29 7FD000h 7FDFFFh SA125 SS28 7FC000h 7FCFFFh SA124 SS27 7FB000h 7FBFFFh SA123 SS26 7FA000h 7FAFFFh SA122 SS25 ...
Page 22
... S25FL064P_00_02 July 2, 2009 ...
Page 23
... READ command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. CS# 0 Mode 3 SCK Mode 0 SI Hi-Z SO July 2, 2009 S25FL064P_00_02 detail the READ command sequence. The first address byte specified Figure 9.1 Read Data Bytes (READ) Command Sequence ...
Page 24
... Bit Address S25FL064P ) presented at the SCK SCK and Table 9.1 on page 22. The first address Dummy Byte MSB MSB DATA OUT 1 S25FL064P_00_02 July 2, 2009 DATA OUT 2 ...
Page 25
... Dual Output Read command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. CS SCK SI/IO0 Hi-Z SO/IO1 July 2, 2009 S25FL064P_00_02 the falling edge of SCK. SCK Figure 9.3 Figure 9.3 Dual Output Read Instruction Sequence 2 5 ...
Page 26
... SCK and Table 9.1 on page 22. The first SI Switches from Input to Output DATA DATA DATA DATA OUT 1 OUT 2 OUT 3 OUT 4 *MSB S25FL064P_00_02 July 2, 2009 ...
Page 27
... Figure 9.5 DUAL I/O High Performance Read Instruction Sequence CS SCK SI/IO0 Hi-Z SO/IO1 July 2, 2009 S25FL064P_00_02 Figure 9.6, thus eliminating eight cycles for the instruction sequence ...
Page 28
... S25FL064P IO0 & IO1 Switches from Input to Output *MSB Byte 2 Byte 1 Figure 9.7 and Table 9.1 on page Figure 9.7). This added feature the S25FL064P_00_02 July 2, 2009 22. ...
Page 29
... SCK SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 Figure 9.8 Continuous QUAD I/O High Performance Instruction Sequence CS# SCK SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 July 2, 2009 S25FL064P_00_02 Figure 9.7 QUAD I/O High Performance Instruction Sequence ...
Page 30
... SCK. The maximum clock frequency for the RDID (9Fh) Figure 9.9 and Table 9.1 on page Instruction Manufacturer / Device Identification High Impedance S25FL064P Table 9.3. 22 652 653 654 Extended Device Information 644 645 646 S25FL064P_00_02 July 2, 2009 655 1 647 ...
Page 31
... July 2, 2009 S25FL064P_00_02 Table 9.2 Manufacturer & Device ID - RDID (JEDEC 9Fh) Manuf. ID Byte 0 01h Table 9.3 Product Group CFI Query Identification String Data 51h 52h Query Unique ASCII string “ ...
Page 32
... Erase Block Region 2 Information (refer to CFI publication 100) 00h 01h 00h 00h Erase Block Region 3 Information (refer to CFI publication 100) 00h 00h 00h 00h Erase Block Region 4 Information (refer to CFI publication 100) 00h 00h S25FL064P Description N S25FL064P_00_02 July 2, 2009 ...
Page 33
... CFI data related to V and time-outs may differ from actual V CC tables to obtain the V range for particular part numbers. Please consult the CC specifications. July 2, 2009 S25FL064P_00_02 Data 50h 52h Query-unique ASCII string “PRI” ...
Page 34
... Read-ID (READ_ID) The READ_ID instruction provides the S25FL064P manufacturer and device information and is provided as an alternative to the Release from Deep Power-Down and Read Electronic Signature (RES), and the JEDEC Read Identification (RDID) commands. The instruction is initiated by driving the CS# pin low and shifting in (via the SI input pin) the instruction code “ ...
Page 35
... Quad Page Program (QPP) completion Parameter Sector Erase (P4E, P8E) completion Sector Erase (SE) command completion Bulk Erase (BE) command completion OTP Program (OTPP) completion July 2, 2009 S25FL064P_00_02 Figure 9.11) sets the Write Enable Latch (WEL) bit which Figure 9 ...
Page 36
... WEL cannot be directly set by the WRR command Table 9.8 S25FL064P Status Register Bit Function 1 = Protects when W#/ACC is low Status Register Write Disable protection, even when W#/ACC is low ...
Page 37
... The Configuration Register originally shows 00h when the device is first shipped from the factory to the customer. (Refer to Figure 9.14 Read Configuration Register (RCR) Instruction Sequence CS SCK High Impedance SO July 2, 2009 S25FL064P_00_02 Section 7.8 on page ...
Page 38
... If not, the Write Registers (WRR) instruction is not MSB High Impedance S25FL064P Table 9.9 shows that W#/ACC must be Figure 9.15 S25FL064P_00_02 July 2, 2009 ...
Page 39
... The Status and Configuration registers originally default to 00h, when the device is first shipped from the factory to the customer. Note: HPM is disabled when the Quad I/O Mode is enabled (Quad bit = 1 in the Configuration Register). W# becomes IO2; therefore, HPM cannot be utilized. July 2, 2009 S25FL064P_00_02 ...
Page 40
... MSB S25FL064P and Table 9.1 on page 22. . The Status Register may Data Byte MSB Data Byte 256 MSB S25FL064P_00_02 July 2, 2009 ...
Page 41
... Quad Input Page Program are identical to standard Page Program. The QPP instruction sequence is shown below. CS# SCK SI/IO0 SO/IO1 W#/ACC/IO2 HOLD#/IO3 CS# SCK SI/IO0 4 5 SO/IO1 W#/ACC/IO2 6 HOLD#/IO3 July 2, 2009 S25FL064P_00_02 Figure 9.18 QUAD Page Program Instruction Sequence Bit Instruction ...
Page 42
... SCK Table 5.1 on page 12 valid address for the P4E or P8E command. 22 Instruction 24 Bit Address MSB S25FL064P S25FL064P_00_02 July 2, 2009 ...
Page 43
... The device only executes a SE command if all Block Protect bits (BP2:BP0) are 0 (see on page 17). Otherwise, the device ignores the command. CS# Mode 3 SCK Mode 0 SI Hi-Z SO July 2, 2009 S25FL064P_00_02 Table 7.3 on page 17 valid address for the SE command. CS# must be Figure 9.20 Sector Erase (SE) Command Sequence ...
Page 44
... Otherwise, the device ignores the command. CS# SCK Figure 9.21 Bulk Erase (BE) Command Sequence Mode Mode 0 Command Hi-Z S25FL064P Figure 9.21 and Table 9.1 . The Status Register may BE Table 7 S25FL064P_00_02 July 2, 2009 ...
Page 45
... The device rejects any DP command issued while it is executing a program, erase, or Write Registers operation, and continues the operation uninterrupted. CS# Mode 3 SCK Mode 0 SI Hi-Z SO July 2, 2009 S25FL064P_00_02 DP, (see Table 16.1 on page 55). Section 9.20 and 9.20.1). ...
Page 46
... after the 8-bit RES command byte. The device transitions RES(max) (see RES Mode 3 Mode 0 Command Hi-Z Deep Power-down Mode S25FL064P Figure 9.23 and Table 9.1 on page Figure 18.1). In the standby mode, the device RES Standby Mode S25FL064P_00_02 July 2, 2009 22. ...
Page 47
... WEL bit before the Clear SR Fail Flags command is executed. The WEL bit will be unchanged after this command is executed. This command also resets the State machine and loads latches SCK SI July 2, 2009 S25FL064P_00_02 for the command sequence and signature value. The Electronic 1 ...
Page 48
... Data Byte MSB “OTP Regions” for details DATA OUT 1 DATA OUT MSB MSB S25FL064P_00_02 July 2, 2009 ...
Page 49
... OTP Read operations outside the valid OTP address range will yield indeterminate data. 10.3 Locking OTP Regions In order to permanently lock the ESN and OTP regions, individual bits at the specified addresses can be set to lock specific regions of OTP memory, as highlighted in Figures July 2, 2009 S25FL064P_00_02 Lock Register ESN2 (Bit 0) ...
Page 50
... N2) 8 bytes (ES N1) Reserved Bit 1 Bit 0 S25FL064P Address B it Locks R egion… 0 OTP1 0x112h 1 OTP2 2 OTP3 3 OTP4 4 OTP5 5 OTP6 6 OTP7 7 OTP8 0 OTP9 0x113h 1 OTP10 2 OTP11 3 OTP12 4 OTP13 5 OTP14 6 OTP15 7 OTP16 0 ESN1 0x100h eserved S25FL064P_00_02 July 2, 2009 ...
Page 51
... Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x214h Note 1. Bit 7 (“X”) at address 0x215h is NOT programmable and will be ignored. July 2, 2009 S25FL064P_00_02 Figure 10.2 OTP Memory Map - Part EGION 10 bytes (OTP31) ...
Page 52
... At power-up, the device is in standby mode (not Deep Power-Down mode) and PU rail decoupled by a suitable capacitor close to the CC Figure 11.1 Power-Up Timing Diagram V cc (max) cc (min Figure 11.2 Power-down and Voltage Drop S25FL064P reaches the allowable values as follows CC rises to the CC CC threshold at power-down, all CC Full Device Access Time S25FL064P_00_02 July 2, 2009 feed. ...
Page 53
... The W#/ACC pin is disabled during Quad I/O mode. Symbol VHH t WC July 2, 2009 S25FL064P_00_02 Table 11.1 Power-Up / Power-Down Voltage and Timing Parameter (minimum operation voltage) (Cut off where re-initialization is needed) (Low voltage for initialization to occur at read/standby) (Low voltage for initialization to occur at embedded) (min ...
Page 54
... Figure 14.2 Maximum Positive Overshoot Waveform +2. +0.5V 2. Table 15.1 Operating Ranges Description Industrial ) A Automotive In-Cabin Voltage Range S25FL064P Rating -65°C to +150°C -0. +0.5V CC 200 Rating –40°C to +85°C –40°C to +105°C 2.7V to 3.6V S25FL064P_00_02 July 2, 2009 ...
Page 55
... Active Power Supply Current I CC5 (BE) I Standby Current SB1 I Deep Power-down Current PD *Typical values are 25°C and V AI July 2, 2009 S25FL064P_00_02 Table 16.1 DC Characteristics (CMOS Compatible) Parameter Test Conditions V = 2. 1.6 mA ...
Page 56
... Input Rise and Fall Times Input Pulse Voltage Input Timing Reference Voltage Output Timing Reference Voltage S25FL064P Input and Output Timing Reference levels Min Max Unit S25FL064P_00_02 July 2, 2009 ...
Page 57
... Full Vcc range (2.7 – 3.6V) & ∞ Regulated Vcc range (3.0 – 3.6V) & Ω Regulated Vcc range (3.0 – 3.6V) & Automotive In-cabin temp range July 2, 2009 S25FL064P_00_02 Figure 18.1 AC Characteristics ...
Page 58
... Figure 18.2 SPI Mode 0 (0,0) Input Timing t t CSS CSH SU:DAT CRT HD:DAT t CFT MSB IN Figure 18.3 SPI Mode 0 (0,0) Output Timing S25FL064P Min Max = CSH CSS LSB DIS LSB OUT S25FL064P_00_02 July 2, 2009 Unit pF pF ...
Page 59
... CS# SCK SO SI HOLD# Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = 1 W# CS# SCK SI Hi-Z SO July 2, 2009 S25FL064P_00_02 Figure 18.4 HOLD# Timing HLCH CHHL t CHHH WPS S25FL064P HHCH ...
Page 60
... LOWER RADIUS OF THE LEAD FOOT. 0.75 9. THIS CHAMFER FEATURE IS OPTIONAL NOT PRESENT, 8˚ THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 15˚ 10. LEAD COPLANARITY SHALL BE WITHIN 0. MEASURED 0˚ FROM THE SEATING PLANE. S25FL064P 3601 \ 16-038.03 \ 8.31.6 S25FL064P_00_02 July 2, 2009 ...
Page 61
... D 6.00 BSC E 8.00 BSC A 0.70 0.75 0.80 A1 0.00 0.02 0.05 L1 0.15 MAX. 0 --- 12 K 0.20 MIN. July 2, 2009 S25FL064P_00_02 (DATUM A) A PIN # R0. SIDE VIEW DATUM A L1 10. TERMINAL TIP e 4. DETAIL "A" NOTES: 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. ...
Page 62
... FAB024 — 24-ball Ball Grid Array ( mm) package S25FL064P S25FL064P_00_02 July 2, 2009 ...
Page 63
... Power-up and Power-down Updated Power-Up / Power-Down Voltage and Timing Table DC Characteristics Updated I Added Automotive In-cabin spec for f AC Characteristics Updated t Physical Dimensions Added BGA package July 2, 2009 S25FL064P_00_02 Description and I CC1 CC3 ...
Page 64
... EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ® ® , the Spansion logo, MirrorBit , MirrorBit S25FL064P ® Eclipse™, ORNAND™, S25FL064P_00_02 July 2, 2009 ...