cs4334-35-38-39 Cirrus Logic, Inc., cs4334-35-38-39 Datasheet - Page 14

• Manufacturer Part Number: cs4334-35-38-39
• Description: 8-pin, 24-bit, 96 Khz Stereo D/a Converters
• Manufacturer: Cirrus Logic, Inc.

14
4.3
4.4
4.5
De-Emphasis
The CS4334 family includes on-chip digital de-emphasis.
equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes
in sample rate, Fs.
The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling edges
of LRCK. This function is available only in the internal serial clock mode.
Initialization and Power-Down
The Initialization and Power-Down sequence flow chart is shown in
the Power-Down State upon initial power-up. The interpolation filters and delta-sigma modulators are reset,
and the internal voltage reference, one-bit digital-to-analog converters and switched-capacitor low-pass fil-
ters are powered down. The device will remain in the Power-Down mode until MCLK and LRCK are present.
Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine
the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is
applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to the quiescent
voltage, V
Output Transient Control
The CS4334 family uses Popguard® technology to minimize the effects of output transients during power-
up and power-down. This technique eliminates the audio transients commonly produced by single-ended
single-supply converters when it is implemented with external DC-blocking capacitors connected in series
with the audio outputs. To make best use of this feature, it is necessary to understand its operation.
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. Af-
ter a short delay of approximately 1000 sample periods, each output begins to ramp towards its quiescent
voltage, V
gradual voltage ramping allows time for the external DC-blocking capacitor to charge to V
blocking the quiescent DC voltage.
To prevent transients at power-down, the device must first enter its power-down state. This is accomplished
by removing MCLK or LRCK. When this occurs, audio output ceases and the internal output buffers are dis-
connected from AOUTL and AOUTR. A soft-start current sink is substituted in place of AOUTL and AOUTR
which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the power to
the device may be turned off, and the system is ready for the next power-on.
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before
turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur
when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-
Q
Q
.
. Approximately 10,000 sample cycles later, the outputs reach V
Figure 9. De-Emphasis Curve (Fs = 44.1kHz)
-10dB
Gain
0dB
dB
Confidential Draft
3.183 kHz
T1=50 µs
F1
3/11/08
10.61 kHz
F2
T2 = 15 µs
Frequency
Figure 9
shows the de-emphasis curve for Fs
Figure
Q
14. The CS4334 family enters
and audio output begins. This
CS4334/5/8/9
Q
, effectively
DS248F5