adn8102 Analog Devices, Inc., adn8102 Datasheet
adn8102
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adn8102 Summary of contents
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... The main application for the ADN8102 is to support switching in chassis-to-chassis applications over CX4 or InfiniBand® cables. The ADN8102 is packaged × 64-lead LFCSP (QFN) package and operates from −40°C to +85°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... ADN8102 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 16 Introduction ................................................................................ 16 Receivers ...................................................................................... 16 Equalization Settings .................................................................. 17 REVISION HISTORY 8/08—Rev Rev. A Changes to Features Section............................................................ 1 Changes to Loss of Signal/Signal Detect Section ...
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... V + 0.4 EE maximum 635 740 800 1.8 V 100 3.3 V 100 1.8 V 1300 3.3 V 1800 CC ADN8102 7 − 1, Max Unit Gbps ps p-p ps rms 2000 mV p-p V p-p V p-p 55 Ω dB 870 mV p-p mV p-p ...
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... ADN8102 Parameter Output Voltage Range Output Current Output Resistance Output Return Loss LOS CHARACTERISTICS Assert Level Deassert Level POWER SUPPLY Operating Range TTI V TTO Supply Current V TTO LOGIC CHARACTERISTICS Input High Input Low Output High, V ...
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... Fall time for both SDA and SCL μs Setup time for a stop condition ns Bus free time between a stop and a start condition pF Capacitance for each I/O pin SU:STA t HIGH Sr 2 Figure Timing Diagram Rev Page BUF HD:STA R t SU:STO P ADN8102 S ...
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... ADN8102 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating 3 0.6 V TTI 0.6 V TTO CC Internal Power Dissipation 4.26 W Differential Input Voltage 2.0 V Logic Input Voltage V − 0.3 V < Storage Temperature Range −65°C to +125°C Lead Temperature 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
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... Negative Supply Loopback Control High Speed Output Complement High Speed Output Positive Supply High Speed Output Complement High Speed Output Output Termination Supply High Speed Output Complement High Speed Output Negative Supply Rev Page ADN8102 48 SCL 47 SDA 46 LOS_B 45 IP_B0 44 IN_B0 43 ...
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... ADN8102 Pin No. Mnemonic Type 28 ON_B3 I/O 29 OP_B3 I/O 30 ENB Control 31 PE_B1 Control 32 PE_B0 Control 33 EQ_B0 Control 34 EQ_B1 Control 35 IN_B3 I/O 36 IP_B3 I/O 37 VEE Power 38 IN_B2 I/O 39 IP_B2 I/O 40 VTTI Power 41 IN_B1 I/O 42 IP_B1 I/O 43 VCC Power 44 IN_B0 I/O 45 IP_B0 I/O 46 LOS_B Digital I/O 47 SDA Control 48 SCL Control 49 ADDR0 Control 50 ADDR1 Control 51 ON_A3 ...
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... PIN PIN ADN8102 AC-COUPLED TP1 EVALUATION BOARD Figure 4. Standard Test Circuit (No Channel) Figure 7. 3.25 Gbps Output Eye, No Channel (TP2 from Figure 4) Figure 8. 3.75 Gbps Output Eye, No Channel (TP2 from Figure 4) Rev Page ADN8102 2 50Ω HIGH SPEED SAMPLING TP2 OSCILLOSCOPE 50ps/DIV 50ps/DIV ...
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... Figure 12. 3.25 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting Figure 13. 3.75 Gbps Output Eye, 40 Inch FR4 Input Channel, Best EQ Setting Rev Page 50Ω CABLES INPUT OUTPUT PIN PIN 50Ω ADN8102 HIGH SPEED AC-COUPLED TP2 TP3 SAMPLING EVALUATION OSCILLOSCOPE BOARD 50ps/DIV (TP3 from Figure 9) 50ps/DIV ...
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... Figure 17. 3.25 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting Figure 18. 3.75 Gbps Output Eye, 30 Meters CX4 Cable, Best EQ Setting Rev Page ADN8102 50Ω CABLES 2 2 INPUT OUTPUT PIN PIN 50Ω ADN8102 HIGH SPEED AC-COUPLED TP3 SAMPLING EVALUATION OSCILLOSCOPE BOARD 50ps/DIV (TP3 from Figure 14) 50ps/DIV (TP3 from Figure 14) ...
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... CABLES 50Ω CABLES INPUT OUTPUT PIN PIN ADN8102 AC-COUPLED TP1 TP2 EVALUATION BOARD Figure 19. Output Pre-Emphasis Test Circuit, FR4 Figure 22. 3.25 Gbps Output Eye, 40 Inch FR4 Output Channel, Figure 23. 3.75 Gbps Output Eye, 40 Inch FR4 Output Channel, Rev Page 50Ω ...
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... AC-COUPLED TP1 TP2 EVALUATION BOARD Figure 24. Output Pre-Emphasis Test Circuit, CX4 Figure 27. 3.25 Gbps Output Eye, 15 Meters CX4 Cable, Figure 28. 3.75 Gbps Output Eye, 15 Meters CX4 Cable, Rev Page ADN8102 50Ω CABLES 2 2 15m CX4 CABLE 50Ω HIGH SPEED TP3 SAMPLING OSCILLOSCOPE ...
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... ADN8102 DATA RATE (Hz) Figure 29. Deterministic Jitter vs. Data Rate 100 0.5 1.0 1.5 DIFFERENTIAL INPUT SWING (V) Figure 30. Deterministic Jitter vs. Differential Input Swing 100 –60 –40 – TEMPERATURE (°C) Figure 31. Deterministic Jitter vs. Temperature ...
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... JITTER (ps) Figure 35. Random Jitter Histogram 100 –60 Figure 36. Rise Time (t Rev Page ADN8102 –40 – TEMPERATURE (°C) )/Fall Time (t ) vs. Temperature R F 100 ...
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... The I/O on-chip termination resistors are terminated to user- settable supplies to support dc coupling in a wide range of logic styles. The ADN8102 supports a wide core supply range; V can be set from 1 3.3 V. These features, together with programmable output levels, allow for a wide range of dc- and ac-coupled I/O configurations ...
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... The ADN8102 receiver incorporates a multizero transfer function continuous time equalizer that provides high frequency boost at 1.875 GHz to compensate meters of CX4 cable or 40 inches of FR4 at 3.75 Gbps. The ADN8102 allows joint control of the equalizer transfer function of the four equalizer channels in a single port through the I interface ...
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... ADN8102 Loss of Signal/Signal Detect An independent signal detect output is provided for all eight input ports of the device. The signal-detect function measures the low frequency amplitude of the signal at the receiver input and compares this measurement with a defined threshold level. If the measurement indicates that the input signal swing is smaller than the threshold for 250 μ ...
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... LOOPBACK The ADN8102 provides loopback on both input ports (Port A: cable interface input, Port B: line card interface input). The external loopback toggle pin, LB, controls the loopback of the Port B input only (board side loopback). When loopback is asserted, valid data continues to pass through the Port B link, but the Port B input signals are also shunted to the Port A output to allow testing and debugging without disrupting valid data ...
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... I C settings overriding the toggle pin control. Similar to the receiver settings, the ADN8102 allows joint control of all four channels in a transmit port. Table 11 summarizes the absolute output level, pre-emphasis level, and high frequency boost for each of the basic control settings and the typical length of the CX4 cable and FR4 trace that each setting compensates ...
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... Rev Page ADN8102 OUT_A/OUT_B Output Level Control 1 0x81 0x81 0x81 0x81 0x81 0x81 0x81 0x91 0x91 0x91 0x91 0x91 0x91 0x91 0x92 0x92 0x92 0x92 0x92 0x92 0x92 0xA2 ...
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... ADN8102 V (mV) V Peak (mV) PE (dB 450 450 0.00 450 550 1.74 450 650 3.19 450 750 4.44 450 850 5.52 450 950 6.49 450 1050 7.36 500 500 0.00 500 600 1.58 500 700 2.92 500 800 4.08 500 900 5.11 500 1000 6.02 500 1100 6.85 550 550 0.00 550 650 1.45 550 750 2.69 550 850 3 ...
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... The TxHeadroom bits should only be set high when V exceeds the value listed in Table 14 for a given output swing. CC ΔV OCM p × Figure 41. Simplified Output Voltage Levels Diagram Rev Page ADN8102 VTTO OCM V L VEE ...
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... ADN8102 Signal Levels and Common-Mode Shift for DC- and AC-Coupled Outputs Table 14. Output Levels and Output Compliance Peak TOT OCM (mV) (mA) (mV) Boost (dB) (mV) (V) V and V = 3.3 V TTO CC 200 8 200 1.00 0.00 200 3.2 200 12 300 1.50 3.52 300 3.1 200 16 400 2.00 6.02 400 3 200 20 500 2 ...
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... Output current that sets output level Output current used for PE Total transmitter output current /2 Maximum single-ended output voltage OD /2 Minimum single-ended output voltage OD Table 16. Squelch Programming Name OUT_A/ OUT_B Squelch Control Rev Page ADN8102 Address Data 0xC3, SQUELCH[3:0] DISABLE[3:0] 0xE3 Default 0xFF ...
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... To write data to the ADN8102 register set, a microcontroller any other I C master, needs to send the appropriate control signals to the ADN8102 slave device. The steps that need to be completed are listed as follows, where the signals are controlled by the I master, unless otherwise specified. A diagram of the procedure can be seen in Figure 42. ...
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... In the example, Data 0x49 is read from Address 0x6D of an ADN8102 part with a part address of 0x4B. The part address is seven bits wide. The upper five bits of the ADN8102 are internally set to 10010b. The lower two bits are controlled by the ADDR[1:0] pins ...
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... ADN8102 PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. POWER SUPPLY CONNECTIONS AND GROUND PLANES Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal ...
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... HYST[5] HYST[4] HYST[3] HYST[2] STICKY STICKY REAL-TIME REAL-TIME LOS [1] LOS[0] LOS[3] LOS[2] EQ1[5] EQ1[4] EQ1[3] EQ1[2] EQ2[5] EQ2[4] EQ2[3] EQ2[2] Rev Page ADN8102 Bit 1 Bit 0 Default RESET LB[1] LB[0] 0x00 MODE[1] MODE[0] 0x00 TxH_A1 TxH_A0 0x00 EQ[1] EQ[0] 0x30 THRESH[1] THRESH[0] 0x04 HYST[1] HYST[0] ...
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... ADN8102 Name Address Bit 7 Bit 6 OUT_A 0xC0 Configuration OUT_A 0xC1 PE CTL Output Level SRC Control 1 0xC2 OUT_A Output Level Control 0 OUT_A 0xC3 Squelch Control OUT_B 0xE0 Configuration OUT_B 0xE1 PE CTL Output Level SRC Control 1 OUT_B 0xE2 Output Level Control 0 OUT_B 0xE3 ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Rev Page 0.30 0.25 0.18 PIN 1 INDICATOR 6.15 6.00 SQ EXPOSED PAD 5.85 (BOTTOM VIEW 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-64-2 CP-64-2 ADN8102 ...
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... ADN8102 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...