adn8102 Analog Devices, Inc., adn8102 Datasheet - Page 19

• Manufacturer Part Number: adn8102
• Description: 3.75 Gbps Quad Bidirectional Cx4 Equalizer
• Manufacturer: Analog Devices, Inc.

ADDR[1:0]
LOOPBACK
The ADN8102 provides loopback on both input ports (Port A:
cable interface input, Port B: line card interface input). The external
loopback toggle pin, LB, controls the loopback of the Port B input
only (board side loopback). When loopback is asserted, valid
data continues to pass through the Port B link, but the Port B
input signals are also shunted to the Port A output to allow testing
and debugging without disrupting valid data. This loopback, as
well as loopback of the Port A input (cable side loopback), can
be programmed through the I
controlled through the I
Bit 1 of the global configuration control register (Register 0x02).
Table 10. Global Configuration Register, Loopback Controls
Name
Global Configuration Control
Ox_A[3:0]
Ix_B[3:0]
RESET
SDA
SCL
LB
EQUALIZATION
PRE-EMPHASIS
TRANSMIT
RECEIVE
EQ
PE
CABLE SIDE LOOPBACK
CONTROL LOGIC
2
C interface by writing to Bit 0 and
PRE-EMPHASIS
EQUALIZATION
TRANSMIT
RECEIVE
PE
EQ
2
C interface. The loopbacks are
Ox_B[3:0]
LOS_A
Ix_A[3:0]
EQ_A[1:0]
PE_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB
Address
0x02
ADDR[1:0]
Ox_A[3:0]
Ix_B[3:0]
RESET
SDA
SCL
LB
Bit 7
Figure 39. Loopback Modes of Operation
PRE-EMPHASIS
EQUALIZATION
TRANSMIT
RECEIVE
EQ
PE
BOARD SIDE LOOPBACK
Rev. A | Page 19 of 32
Bit 6
CONTROL LOGIC
Bit 5
PRE-EMPHASIS
EQUALIZATION
Bit 1 represents loopback of the Port A inputs to the Port B
outputs (cable side loopback). Bit 0 represents loopback of the
Port B inputs to the Port A outputs (board side loopback), with
high representing loopback for both bits. Bit 0 is also controlled
through the LB pin with I
input ports can be looped back simultaneously (full loopback)
by writing high to both Bit 0 and Bit 1, but in this case, valid
data is disrupted on each channel. Figure 39 illustrates the three
loopback modes.
TRANSMIT
RECEIVE
PE
EQ
Bit 4
Ox_B[3:0]
LOS_A
Ix_A[3:0]
EQ_A[1:0]
PE_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB
Bit 3
ADDR[1:0]
Ox_A[3:0]
Ix_B[3:0]
RESET
SCL
SDA
LB
Bit 2
2
C data overwriting the pin state. Both
PRE-EMPHASIS
EQUALIZATION
TRANSMIT
RECEIVE
EQ
PE
Bit 1
LB[1]
FULL LOOPBACK
CONTROL LOGIC
Bit 0
LB[0]
PRE-EMPHASIS
EQUALIZATION
TRANSMIT
RECEIVE
PE
ADN8102
EQ
Default
0x00
Ox_B[3:0]
LOS_A
Ix_A[3:0]
EQ_A[1:0]
PE_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB