ir3084u International Rectifier Corp., ir3084u Datasheet
ir3084u
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ir3084u Summary of contents
Page 1
... The XPhase that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. The IR3084U is based on the IR3084 VR10 Control IC, but incorporates the following modifications; • Supports VR11 7-bit VID, VR10 7-bit extended VID, and Opteron/Athlon64 5-bit VID codes • ...
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... VID5 3 VID6 RVSETPT1 1 124 VIDSEL 14 VSETPT RVSETPT 21 124 VCC 13 OCSET ROCSET 26 12.7K SS/DEL 12 VDAC CSS/DEL 0.1uF 11 VOSNS-- LGND ROSC ROSC 30. IR3084U EA R1331 Q4 VREG_12V_FILTERED 1 CJD200 VGDRIVE C204 C135 0.1uF 1uF VR_RDY ISHARE RMP VBIAS RVGDRV CVGDRV 97.6K 10nF VDAC RVDAC 3.5 CVDAC 33nF 9/14/2005 ...
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... IR3084U I SINK 1mA 1mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 5mA 1mA 20mA 5mA 10mA 50mA 1mA 1mA 50mA 1mA 1mA 20mA 1mA 9/14/2005 ...
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... Page TEST CONDITION ≤ T ≤ 100 ≤ T ≤ 100 ≤ T ≤ 100 C J IR3084U ≤ 16V, −0.3V ≤ VOSNS- ≤ 0.3V, MIN TYP MAX UNIT −0.5 0.5 % − − 104 113 122 μA μA 92 100 ...
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... VID Sample Delay VR10/VR11 mode only Comparator Threshold SS/DEL Discharge Comparator Threshold Page TEST CONDITION MIN −2.0 5.6 0.20 0.35 −10 −9.0 0 6.6 −35 −10 −53.5 1.2 0.8 0.2 0.5 0.7 150 0. 9.5 20 3.6 IR3084U TYP MAX UNIT −0.2 1.0 µA 12.5 19.4 KΩ 0.35 0.50 V 0.60 0.85 V − −6.8 −4.0 mA 0.85 4 MHz 10 V/μs 6.9 7.2 V −20 − ...
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... V(REGSET) < VCC – 1.5V, Note 1 Dropout Voltage I(REGDRV) = 10mA, Note 1 Page TEST CONDITION MIN 800 700 70 1.11 1. 450 70 10 100 250 50 1.2 200 −112 −12 10 0.4 IR3084U TYP MAX UNIT 150 300 μA 850 900 mV 750 800 mV 100 130 mV 1.23 1.35 V 1.17 1. ...
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... ERROR 200 OHM FB AMP VSETPT OCSET VDAC IOCSET IROSC IROSC ROSC BUFFER CURRENT AMP + SOURCE GENERATOR - ROSC + 1.2V - VOSNS- Figure 1 – System Set Point Test Circuit IR3084U MIN TYP MAX UNIT 9.3 9.9 10.3 V 8.5 9.1 9.5 V 550 800 1000 −1.45 −1.1 −0.75 mA 200 OHM ...
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... Open Collector output that drives low during start-up and when any external fault 27 VRRDY occurs. Connect external pull-up resistor. Enable Input. A logic low applied to this pin puts the IC into Fault mode. This pin 28 ENABLE has a 100K pull-down resistor to GND. Page IR3084U DESCRIPTION 9/14/2005 ...
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... PHASE FAULT CURRENT SHARE IR3086 PHASE IC CCS RCS PHASE FAULT CURRENT SHARE IR3086 PHASE IC CCS RCS ADDITIONAL PHASES Figure 2 – System Block Diagram IR3084U VR READY PHASE FAULT VR HOT VR FAN CIN VOUT SENSE+ VOUT+ COUT VOUT- VOUT SENSE- INPUT/OUTPUT 9/14/2005 ...
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... RRAMP2 PWMRMP ENABLE RAMP SLOPE RPWMRMP ADJUST RAMP DISCHARGE SCOMP CLAMP CPWMRMP SHARE CSCOMP ADJUST ERROR AMP + ISHARE 20mV 10K - DACIN Figure 3 – IR3084U PWM Block Diagram IR3084U PWM LATCH GATEH S RESET DOMINANT - R GATEL + + O% DUTY - CYCLE COMPARATOR X 0.91 CURRENT CSIN+ SENSE AMP ...
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... An additional advantage is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Page 50% RAMP DUTY CYCLE SLOPE = 80mV / % DC SLOPE = 1.6mV / ns @ 200kHz SLOPE = 8.0mV / ns @ 1MHz Figure 4 – 8 Phase Oscillator Waveforms IR3084U 9/14/2005 ...
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... THRESHOLD DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) Figure 5 – PWM Operating Waveforms IR3084U ) DUTY CYCLE DECREASE DUE TO LOAD STEADY-STATE DECREASE (BODY BRAKING) OR FAULT OPERATION (VCC UV, VCCVID UV, OCP, VID=11111X 9/14/2005 ...
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... PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact with the output voltage loop. Page CSA CO IR3084U 9/14/2005 ...
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... ISOURCE 0.6V 1.95V - - ISINK - VID = 1.1V BOOT 1.2V VBIAS - VBIAS 6.9V REGULATOR + IROSC ROSC BUFFER CURRENT AMP SOURCE + GENERATOR IROSC IREGSET - VCC Figure 7 – IR3084U Block Diagram IR3084U S 0.6V NO CPU LATCHED FAULT 0.35V LATCH - S R IIN + VID PRECONDITIONING FAULT LATCH LATCH VDRP R - AMP + + OC ...
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... IR3084U VID0 VID5 VID6 Voltage 1.20000 1.19375 1.18750 1.18125 1.17500 ...
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... Table 2 – VR11 7-bit VID Table IR3084U Dec (VID7:VID0) Voltage 01000000 1.21250 01000001 1.20625 01000010 1.20000 01000011 1.19375 01000100 1.18750 01000101 1.18125 01000110 1.17500 01000111 1.16875 01001000 1.16250 01001001 1.15625 01001010 1 ...
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... OFF IR3084U 9/14/2005 ...
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... Dynamic VID Operation The IR3084U can accept changes in the VID code while operating and vary the DAC voltage accordingly. The sink/source capability of the VDAC buffer amp is programmed by the external resistor that sets the oscillator frequency (Rosc). The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and the VOSNS− ...
Page 19
... Start-up Modes The IR3084U has a programmable soft-start function to limit the surge current during converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay, and hiccup mode timing. A charge current of 70µ ...
Page 20
... Voltage GND (<0.6V) FLOAT (>1.8V) 6.49K to GND Opteron/Athlon64 (0.9V<VIDSEL<1.7V) Table 4: Controller Functionality versus VIDSEL Voltages Page 1.1V Boot Ignore NO CPU VID Voltage During Codes During Table Startup? VR10 YES VR11 YES NO IR3084U Latch NO CPU Fault Code? Startup? YES YES YES YES NO NO 9/14/2005 ...
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... SOFT START TIME SAMPLE 1.3ms (TD4+TD5) 1.6ms (TD2) DELAY 1.0ms (TD3) DYNAMIC VID TIME 200us (TD4) VID SETTING SOFT START TIME VR_RDY DELAY 1.8ms 2.3ms IR3084U 9.1V UVLO VDAC NORMAL POWER-DOWN OPERATION (VCC UVL INITIATES FAULT MODE) 9.1V UVLO POWER-DOWN (VCC UVL NORMAL ...
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... The SS/DEL capacitor will discharge down to 0.215V through a 6.5µA current source. If the fault has cleared when SS/DEL falls to 0.215V then the fault latch will be reset by the discharge comparator allowing a normal start-up sequence to occur VID = FAULT condition is latched it can only be cleared by cycling power to the IR3084U on and off. SS/DEL 3.75V (3 ...
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... Phase ICs thus providing UVLO protection for them as well. UVLO at the Phase ICs is a function of the Error Amplifier’s output voltage. When the IR3084U is in UVLO, the Error Amplifier is disabled and EAOUT very low voltage (<200mV) thus preventing the Phase ICs from becoming active. ...
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... System Reference Voltage (VBIAS) The IR3084U supplies a 6.8V/6mA precision reference voltage from the VBIAS pin. The oscillator ramp trip points are based on the VBIAS voltage so it should be used to program the Phase ICs phase delay to minimize phase errors. Phase IC Gate Driver Bias Regulator / VRHOT Comparator ...
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... I(VDAC SOURCE) (uA) I(VDAC SINK) (uA) 150 100 1.E+01 1.E+02 IR3084U Figure 14: I(OCSET) versus ROSC ROSC (Kohms ROSC (Kohms) Figure 18: IR3084 Error Amplifier Bode Plot 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Frequency (Hz) 9/14/2005 ...
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... VCC 13 OCSET R31 C131 10 26 0.1uF SS/DEL 12 VDAC CSS/DEL 0.1uF 11 VOSNS-- LGND ROSC ROSC 10 22 30.1K Figure 19 – IR3084U/3086 5 Phase VRM/EVRD 11 Converter Page R1332 Q8 1 CJD200 C205 C137 0.1uF 1uF R138 2K C136 C90 0.1uF 100pF RVGDRV CVGDRV 97.6K 10nF RVSETPT2 124 ROCSET 12 ...
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... DESIGN PROCEDURES – IR3084U and IR3086 Chipset IR3084U EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3084 generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which is set by the external resistor R according to the curve in Figure 13 on page ...
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... CSA the current sense amplifier in the phase IC is the sum of input offset ) ( ) ∗ − ∗ − − CS CSIN CS . See Figure 15 on page 25. OSC + C IR3084U DRP voltage and output voltage at no load. DAC ( TOFST CSA V O_NLOFST (6) (7) (8) 9/14/2005 ...
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... SS / DEL − − = − DEL TD 4 − 100 DEL − IR3084U SS/DEL ) from the data CHG 2 (9) ⎞ RFB ⎟ + RDRP ⎠ ∞ ). (10) ∞ ). (11 (12) (13) 9/14/2005 . ...
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... OCSET pin, changes with switching frequency setting MIN ∗ ∗ CS_TOFST I OCSET ∗ ∗ ∗ /( IR3084U and room L_MAX (14) is calculated from Equation (15). (15) is the LIMIT is the ratio of inductor peak current to P (16) (17) 9/14/2005 ...
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... IN DAC IN and Resistors R and R CS+ CS+ . Pre−select the capacitor C L CS− The resistor R is determined by the ratio of the bias current from the . CS− value is needed. CS+ IR3084U PWMRMP should be connected to RAMP (18) − − DAC PWMRMP CS− and capacitor CS+ and calculate R CS+ ...
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... If the resistor R determined as: ∗ PHASEx PHASEx1 R PHASEx2 − PHASEx Page and R HOTSET1 HOTSET2 1.241 is pre−selected, R HOTSET1 HOTSET2 and R PHASE2 PHASEx1 IR3084U (ºC) of phase IC. J (21) can be calculated as follows. (22) is pre-selected, the resistor R PHASEx2 (23) 9/14/2005 is ...
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... RA ) PHASEx ) and R and connect RMPIN+ or RMPIN− between R PHASEx2 , PHASEx1 ∗ ∗ BIAS PHASEx1 − V HOTSET *R PHASEx1 IR3084U R and R PHASE1, PHASE2 PHASE3 and R and connect HOTSET pin PHASEx2 and R PHASEx2 PHASEx3, (24) (25) , connect PHASEx PHASEx2 (26) (27) 9/14/2005 and ...
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... Page CCP1 RFB VO+ CCP RFB1 CFB - RDRP VDRP EAOUT EAOUT CDRP + (b) Type III compensation C can be determined by Equations (28) and (29). CP and PWMRMP IR3084U CCP1 RCP CCP FB - EAOUT EAOUT VDAC + (28) (29) is CP1 9/14/2005 ...
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... FB1 and determine the SCOMP + * 2π CS_ROOM LE V 2π PWMRMP − DAC I DAC IR3084U (30) (31) from Equations (32) and (33). DRP (32) (33) ) based on the (35) 9/14/2005 (34) ...
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... Figure 13 on page 25. In this design, OSC to be 30.1kΩ. OSC and Resistor R VDAC VDAC − Choose C − − − 15 3.2* 0.5 3.5Ω − (33*10 ) − 2.7mV/uS − 9 IR3084U =30.1kΩ) is 80uA. Calculate the OSC = 33nF VDAC = 30.1KΩ. The VDAC positive OSC 9/14/2005 ...
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... 3984 * . 0 015 . 0 0195 * . − − 3984 . 0 1710 . 0 0195 . 0 00494 = 123 5 . ohms − IR3084U = and R , respectively. For this CS+ CS− ) Ω 574 mV and RDRP VSETPT bias current is VSETPT − − 574 * ...
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... V = − − − − 100 * 250 us − IR3084U 787 1 . ohms − 0988 uF or 0.1uF ⎞ ⎟ 787 ⎠ − 6 ⎛ ⎞ 324 + * ⎜ ⎟ − ⎝ 324 787 ⎠ ...
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... MIN + + ∗ CS_TOFST I OCSET − ∗ 574 * 10 ) − IR3084U − ∗ − 3850*10 (100 25 − ∗ − ∗ − 1470*10 (101 25 42.5µA with OCSET − ∗ ∗ ∗ 400 ...
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... R and R HOTSET1 HOTSET2 − ∗ 241 . 116 . 1 241 ∗ Ω − IR3084U PWMRMP − − DAC PWMRMP = 15.8k Ω − − ln(12 1.30 0.8)] CS− CS− = 6.19kΩ CS− choose R =20.0kΩ, HOTSET1 9/14/2005 and , using ...
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... Choose R =162Ω FB1 162 IR3084U Ω =13.2kΩ, R =5.48kΩ, PHASE32 − − 220 * 560 * − − − 015 130 * * ...
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... O CI − π 5600 π − − 130 IR3084U =4kHz and calculate FMI and − 400 * 0105 − − − ...
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... GND R REGSET GND C SS/DEL Page OSC OCSET VDAC VDAC VCC LGND REGFB REGDRV REGSET SS/DEL VRRDY ENABLE To SYSTEM IR3084U , C and R . Avoid using any SS/DEL CC/DEL R SETPT R OCSET VSETPT OCSET R VDAC VDAC ROSC R OSC VOSNS- VID0 C VDAC VID1 To Voltage ...
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... Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. • The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via. Page IR3084U 9/14/2005 ...
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... Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper) • A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. Page IR3084U 9/14/2005 ...
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... The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page IR3084U 9/14/2005 ...
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... C/W, θ C/W JC Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. Visit us at www.irf.com for sales contact information. IR3084U TAC Fax: (310) 252-7903 9/14/2005 ...