ir3084u International Rectifier Corp., ir3084u Datasheet - Page 10

• Manufacturer Part Number: ir3084u
• Description: Xphasetm Vr10, Vr11 & Opteron/athlon64 Control Ic
• Manufacturer: International Rectifier Corp.

PWM Control Method
The PWM block diagram of the XPhase
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to
program the slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp
slope will change with the input voltage and automatically compensate for changes in the input voltage. The input
voltage can change due to variations in the silver box output voltage or due to drops in the PCB related to
changes in load current.
Frequency and Phase Timing Control
The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external
resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of
approximately 5V and 1V. This signal is used to program both the switching frequency and phase timing of the
Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the
VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the
oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the
PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors.
Figure 4 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be
used for synchronization by swapping the RAMP + and – pins.
+
-
50%
DUTY
CYCLE
IOFFSET
VBIAS
REGULATOR
CONTROL IC
RAMP GENERATOR
Page 10 of 47
IROSC
+
-
ERROR
AMP
VDAC
VPEAK
VVALLEY
+
-
VDRP
AMP
VDRP
IIN
RMPOUT
VBIAS
VOSNS-
VDAC
VSETPT
EAOUT
FB
RVSETPT
RVFB
RDRP
Figure 3 – IR3084U PWM Block Diagram
TM
architecture is shown in Figure 3. Feed-forward voltage mode control
RRAMP2
RRAMP2
RRAMP1
RPWMRMP
CPWMRMP
RRAMP1
RPWMRMP
CPWMRMP
CSCOMP
CSCOMP
RAMPIN+
RAMPIN-
PWMRMP
RAMPIN+
RAMPIN-
PWMRMP
SCOMP
ISHARE
DACIN
BIASIN
SCOMP
ISHARE
DACIN
BIASIN
EAIN
EAIN
RAMP
SLOPE
ADJUST
RAMP
SLOPE
ADJUST
+
-
+
-
SYSTEM
REFERENCE
VOLTAGE
SYSTEM
REFERENCE
VOLTAGE
SHARE
ADJUST
ERROR
AMP
10K
SHARE
ADJUST
ERROR
AMP
10K
CLOCK
PULSE
GENERATOR
CLOCK
PULSE
GENERATOR
+
-
+
-
20mV
20mV
RAMP
DISCHARGE
CLAMP
RAMP
DISCHARGE
CLAMP
PWM
COMPARATOR
ENABLE
PWM
COMPARATOR
ENABLE
PHASE IC
PHASE IC
-
+
-
+
+
-
+
-
DOMINANT
DOMINANT
S
RESET
R
O% DUTY
CYCLE
COMPARATOR
S
RESET
R
O% DUTY
CYCLE
COMPARATOR
PWM
LATCH
PWM
LATCH
CURRENT
SENSE
AMP
X34
CURRENT
SENSE
AMP
X34
X
0.91
X
0.91
+
-
+
-
GATEH
GATEL
GATEH
GATEL
CSIN+
CSIN-
CSIN+
CSIN-
CCS
CCS
RCS
RCS
IR3084U
9/14/2005
COUT
VIN
VOSNS+
VOUT
GND
VOSNS-