ltc1598l Linear Technology Corporation, ltc1598l Datasheet - Page 14

• Manufacturer Part Number: ltc1598l
• Description: 4- And 8-channel, 3v Micropower Sampling 12-bit Serial I/o A/d Converters
• Manufacturer: Linear Technology Corporation

APPLICATIONS
LTC1594L/LTC1598L
MUXOUT/ADCIN Loop Economizes
Signal Conditioning
The MUXOUT and ADCIN pins of the LTC1594L/LTC1598L
form a very flexible external loop that allows Program-
mable Gain Amplifier (PGA) and/or processing analog
input signals prior to conversion. This loop is also a cost
effective way to perform the conditioning, because only
one circuit is needed instead of one for each channel.
In the Typical Applications section, there are a few
examples illustrating how to use the MUXOUT/ADCIN loop
to form a PGA and to antialias filter several analog inputs.
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 160 A and automatic
shutdown between conversions, the LTC1594L/
LTC1598L achieve extremely low power consumption
over a wide range of sample rates (see Figure 6). The auto
shutdown allows the supply current to drop with reduced
sample rate. Several things must be taken into account to
achieve such a low power consumption.
Shutdown
The LTC1594L/LTC1598L are equipped with automatic
shutdown features. They draw power when the CS pin is
low. The bias circuits and comparator of the ADC powers
down and the reference input becomes high impedance at
the end of each conversion leaving the CLK running to
clock out the LSB first data or zeroes (see Figures 1 and 2).
When the CS pin is high, the ADC powers down completely
14
COM = GND
MUXOUT
ADCIN =
CSMUX
CH0 TO
CSADC
D
CLK
CH7
OUT
D
IN
B4
B3 B2
EN
U
D2
B1 B0
D1
D0
INFORMATION
U
t
SMPL
t
ON
t
suCS
Figure 5. Use Separate Chip Selects to Maximize Sample Rate
NULL
BIT
W
B11
B10
DON’T CARE
B9
B8
B7
t
U
CONV
B6
B5
B4
B3 B2
EN
leaving the CLK running to clock the input data word into
MUX. If the CS, D
input logic buffers will draw currents. These currents may
be large compared to the typical supply current. To obtain
the lowest supply current, run the CS, D
rail-to-rail.
D
Capacitive loading on the digital output can increase
power consumption. A 100pF capacitor on the D
can add more than 50 A to the supply current at a 200kHz
clock frequency. An extra 50 A or so of current goes into
charging and discharging the load capacitor. The same
goes for digital lines driven at a high frequency by any
logic. The (C)(V)(f) currents must be evaluated and the
troublesome ones minimized.
OUT
D2
B1 B0
Figure 6. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate
D1
Loading
D0
1000
100
t
SMPL
10
t
ON
1
t
suCS
0.1
NULL
T
V
V
f
BIT
CLK
A
CC
REF
= 25 C
IN
= 2.7V
B11
= 200kHz
= 2.5V
and CLK are not running rail-to-rail, the
SAMPLE FREQUENCY (kHz)
B10
DON’T CARE
B9
1
B8
B7
t
CONV
B6
10
B5
B4
1594L/98L G01
B3 B2
IN
EN
100
and CLK pins
D2
B1 B0
D1
1594L/98L F05
OUT
D0
15948lfb
pin