st62t62b

Manufacturer Part Numberst62t62b
Description8-bit Otp/eprom Mcus With A/d Converter, Auto-reload Timer And Eeprom
ManufacturerSTMicroelectronics
st62t62b datasheet
 


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R
A/D CONVERTER, AUTO-RELOAD TIMER AND EEPROM
3.0 to 6.0V Supply Operating Range
8 MHz Maximum Clock Frequency
-40 to +125° C Operating Temperature Range
Run, Wait and Stop Modes
5 Interrupt Vectors
Look-up Table capability in Program Memory
Data Storage in Program Memory:
User selectable size
Data RAM: 128 bytes
Data EEPROM: 64 bytes (none on ST62T52B)
User Programmable Options
9 I/O pins, fully programmable as:
– Input with pull-up resistor
– Input without pull-up resistor
– Input with interrupt generation
– Open-drain or push-pull output
– Analog Input
5 I/O lines can sink up to 20mA to drive LEDs or
TRIACs directly
8-bit Timer/Counter with 7-bit programmable
prescaler
8-bit Auto-reload Timer with 7-bit programmable
prescaler (AR Timer)
Digital Watchdog
8-bit A/D Converter with 4 analog inputs
On-chip Clock oscillator can be driven by Quartz
Crystal Ceramic resonator or RC network
User configurable Power-on Reset
One external Non-Maskable Interrupt
ST626x-EMU2 Emulation and Development
System (connects to an MS-DOS PC via a
parallel port)
DEVICE SUMMARY
EPROM
OTP
DEVICE
(Bytes)
(Bytes)
ST62T52B
1836
ST62T62B
1836
ST62E62B
1836
April 1998
ST62T62B/E62B
8-BIT OTP/EPROM MCUs WITH
(See end of Datasheet for Ordering Information)
EEPROM
-
64
64
ST62T52B
PDIP16
PSO16
CDIP16W
Rev. 2.4
1/68
1

st62t62b Summary of contents

  • Page 1

    ... ST626x-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port) DEVICE SUMMARY EPROM OTP DEVICE (Bytes) (Bytes) ST62T52B 1836 ST62T62B 1836 ST62E62B 1836 April 1998 ST62T62B/E62B 8-BIT OTP/EPROM MCUs WITH (See end of Datasheet for Ordering Information) EEPROM - 64 64 ST62T52B PDIP16 PSO16 CDIP16W Rev. 2.4 1/68 1 ...

  • Page 2

    ... ST62T52B / ST62T62B/E62B . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.2 Program Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3.3 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.4 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3.5 Data Window Register (DWR 1.3.6 Data RAM/EEPROM Bank Register (DRBR 1.3.7 EEPROM Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.1 Option Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4.3 . EEPROM Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 ...

  • Page 3

    Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    ... The ST62E62B is the erasable EPROM version of the ST62T62B device, which may be used to em- ulate the ST62T52B and ST62T62B devices as well as the ST6252B and ST6262B ROM devices. OTP and EPROM devices are functionally identi- cal ...

  • Page 5

    ... PB6/ARTIMin and PB7/ARTI- ST62T52B ST62T62B/E62B Mout are either Port B I/O bits or the Input and Output pins of the ARTimer. Reset state of PB2-PB3 pins can be defined by option either with pull-up or high impedance ...

  • Page 6

    ... ST62T52B ST62T62B/E62B 1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Figure 3. Memory Addressing Diagram PROGRAM SPACE 0000h PROGRAM MEMORY 0FF0h INTERRUPT & RESET VECTORS ...

  • Page 7

    ... EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for SGS-THOMSON, to gain access to the OTP contents. Returned parts with a protection set can therefore not be ac- cepted. ST62T52B ST62T62B/E62B Figure 4. ST62T52B/T62B Program Memory Map 0000h * RESERVED 087Fh ...

  • Page 8

    ... ST62T52B ST62T62B/E62B MEMORY MAP (Cont’d) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up OTP/EPROM. ...

  • Page 9

    ... ST62T52B ST62T62B/E62B DWR5 DWR4 DWR3 DWR2 DWR1 DWR0 PROGRAM SPACE ADDRESS READ DATA SPACE ADDRESS : 40h-7Fh IN INSTRUCTION DATA SPACE ADDRESS : 59h VR01573C 0 9/68 9 ...

  • Page 10

    ... ST62T52B ST62T62B/E62B MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM (DRBR) Address: E8h — Write only 7 DRBR - - - - 4 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit 1-3. Not used Bit 0. DRBR0. This bit, when set, selects EEP- ROM page 0 ...

  • Page 11

    ... EECTL it must also write to the image register. The image regis- ter must be written to first so that interrupt oc- curs between the two instructions, the EECTL will not be affected ST62T52B ST62T62B/E62B Dataspace addresses. Banks 0 and 38h-3Fh 30h-37h 28h-2Fh ...

  • Page 12

    ... ST62T52B ST62T62B/E62B MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle resetting E2PAR2 without programming the EEPROM ...

  • Page 13

    ... PC menu (PC driven Mode) or automatically (stand-alone mode) 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V 0 programming flow of the ST62T62B is described in the User Manual of the EPROM Programming - Board. The MCUs can be programmed with the ST62E6xB EPROM programming tools available from SGS-THOMSON ...

  • Page 14

    ... ST62T52B ST62T62B/E62B 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6; the controller being externally ...

  • Page 15

    ... Switching between the three sets of flags is per- formed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is ST62T52B ST62T62B/E62B automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hard- ware stack which eliminates the need for a stack pointer ...

  • Page 16

    ... ST62T52B ST62T62B/E62B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic resonator, or with an external resistor (R ). NET Figure 8. illustrates various possible oscillator con- ...

  • Page 17

    ... OSCR it must write also to the image register. The image register must be written first inter- rupt occurs between the two instructions the OSCR is not affected. Division Ratio OSCILLATOR DIVIDER RS0, RS1 ST62T52B ST62T62B/E62B POR Core : 13 Timer f INT Watchdog : 12 ADC AR Timer : 1 ...

  • Page 18

    ... ST62T52B ST62T62B/E62B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required ...

  • Page 19

    ... RETI instruction. If, however, a pending inter- rupt is present, it will be serviced. Figure 11. Reset and Interrupt Processing and DD RESET VECTOR rises INITIALIZATION ROUTINE f OSC RESET ST62T52B ST62T62B/E62B RESET JP:2 BYTES/4 CYCLES JP RETI: 1 BYTE/2 CYCLES RETI VA00181 ST6 CK INTERNAL RESET COUNTER RESET VA0200B 19/68 19 ...

  • Page 20

    ... ST62T52B ST62T62B/E62B RESETS (Cont’d) Table 6. Register Reset Status Register Oscillator Control Register EEPROM Control Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR TIMER Mode Control Register AR TIMER Status/Control 1 Register AR TIMER Status/Control 2Register AR TIMER Compare Register ...

  • Page 21

    ... Watchdog counter is frozen and the CPU en- ters STOP mode. Table 7 Recom- When the MCU exits STOP mode (i.e. when an in- terrupt is generated), the Watchdog resumes its activity. “EXTERNAL STOP MODE” & “HARDWARE WATCHDOG” “SOFTWARE WATCHDOG” “HARDWARE WATCHDOG” ST62T52B ST62T62B/E62B Recommended Options 21/68 21 ...

  • Page 22

    ... ST62T52B ST62T62B/E62B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register This register is set to 0FEh on Reset: bit C is cleared to “0”, which disables the Watchdog; the timer downcounter bits T5, and the SR bit are all set to “ ...

  • Page 23

    ... The software activation option should be chosen only when the Watchdog counter used as a timer. To ensure the Watchdog has not been un- expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, WD, #+3 ldi WD, 0FDH ST62T52B ST62T62B/E62B 23/68 23 ...

  • Page 24

    ... ST62T52B ST62T62B/E62B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions are ex- ecuted after activation, before the Watchdog can generate a Reset ...

  • Page 25

    ... Table 9. Interrupt Option Register Description (FF4h-FF5h) (FF2h-FF3h) GEN (FF0h-FF1h) ESB LES OTHERS ST62T52B ST62T62B/E62B SET Enable all interrupts CLEARED Disable all interrupts Rising edge mode on inter- SET rupt source #2 Falling edge mode on inter- CLEARED ...

  • Page 26

    ... ST62T52B ST62T62B/E62B IINTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call procedure, indeed the user can consider the inter- rupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred re- sult, the user should save all Data space registers which may be used within the interrupt routines ...

  • Page 27

    ... OVIE OVF: AR TIMER Overflow D5h CPIE CPF: Successful compare EIE EF: Active edge on ARTIMin C0h-C4h ORPAn-DRPAn PAn pin C1h-C5h ORPBn-DRPBn PBn pin C2h-C6h ORPCn-DRPCn PCn pin ST62T52B ST62T62B/E62B sources available on Table 10 Interrupt Masked Interrupt Source vector I Vector 4 Vector 4 Vector 3 Vector 1 Vector 1 Vector 2 27/68 ...

  • Page 28

    ... ST62T52B ST62T62B/E62B INTERRUPTS (Cont’d) Figure 17. Interrupt Block Diagram FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B Bits PORT C PBE Bits AR TIMER TIMER1 V DD NMI 28/ CLK Q CLR I Start MUX 1 1 IOR REG. C8H, bit 6 FF CLK Q CLR ...

  • Page 29

    ... Watchdog), the MCU enters a normal reset proce- dure interrupt is generated during WAIT mode, the MCU’s behaviour depends on the state ST62T52B ST62T62B/E62B of the processor core prior to the WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following para- graphs ...

  • Page 30

    ... ST62T52B ST62T62B/E62B POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart sequence depends on the original state ...

  • Page 31

    ... RAM cells are needed for port data storage and manipulation. During MCU initialization, all I/O registers are cleared and the input mode with pull- ups and no interrupt generation is selected for all the pins, thus avoiding pin conflicts. DATA DIRECTION REGISTER DATA REGISTER OPTION REGISTER ST62T52B ST62T62B/E62B INPUT/OUTPUT VA00413 31/68 31 ...

  • Page 32

    ... ST62T52B ST62T62B/E62B I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). Table 11 I/O Port Option Selection lustrates the various port configurations which can be selected by user software ...

  • Page 33

    ... Open Drain Output Push-pull Note *. xxx = DDR, OR, DR Bits respectively ST62T52B ST62T62B/E62B outputs advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data regis- ...

  • Page 34

    ... ST62T52B ST62T62B/E62B I/O PORTS (Cont’d) Table 12. I/O Port Option Selections MODE AVAILABLE ON Input PA4-PA5 Reset state( PB0, PB6-PB7 PC2-PC3 Reset state if PULL-UP PB2-PB3, option disabled PA4-PA5 Input PB0,,PB6-PB7 Reset state PC2-PC3 Reset state if PULL-UP option enabled PB2-PB3 Input PA4-PA5 with pull up ...

  • Page 35

    ... Figure 20. Peripheral Interface Configuration of AR Timer ARTIMin ARTIMout ARTIMin/PB6 is connected to the AR Timer input configured through the port registers as any standard pin of port B. To use ARTIMin/PB6 as AR Timer input, it must be configured as input through DDRB. PID ARTIMin DR AR TIMER PID OR PWMOE ARTIMout 1 MUX 0 DR ST62T52B ST62T62B/E62B VR01661G 35/68 35 ...

  • Page 36

    ... ST62T52B ST62T62B/E62B 4.2 TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 Figure 21. shows the Timer Block Diagram. The content of the 8-bit counter can be read/written in the Timer/Counter register, TCR, which can be addressed in Data space as a RAM location at ad- dress 0D3h ...

  • Page 37

    ... TSCR register is cleared. This means that the Timer is stopped (PSI=“0”) and the timer interrupt is disabled. 7-BIT PRESCALER BIT2 BIT3 BIT4 8-1 MULTIPLEXER BIT2 BIT3 BIT4 BIT5 8-BIT COUNTER ST62T52B ST62T62B/E62B BIT5 BIT6 PS0 PS1 PS2 BIT7 BIT6 VA00186 37/68 37 ...

  • Page 38

    ... ST62T52B ST62T62B/E62B TIMER (Cont’d) A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i. write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again ...

  • Page 39

    ... The PWM signal is generated on the ARTIMout pin (refer to the Block Diagram). The frequency of this signal is controlled by the prescaler setting and by the auto-reload value present in the Re- load/Capture register, ARRC. The duty cycle of the PWM signal is controlled by the Compare Register, ARCP. ST62T52B ST62T62B/E62B 39/68 39 ...

  • Page 40

    ... ST62T52B ST62T62B/E62B AUTO-RELOAD TIMER (Cont’d) Figure 23 Timer Block Diagram f INT M f 7-Bit /3 INT U AR PRESCALER X PS0-PS2 CC0-CC1 PB6/ ARTIMin SL0-SL1 EF SYNCHRO 40/68 40 DATA BUS 8 AR COMPARE REGISTER 8 CPF COMPARE 8 OVF 8-Bit LOAD AR COUNTER RELOAD/CAPTURE LOAD REGISTER REGISTER 8 8 DATA BUS ...

  • Page 41

    ... VALUE RELOAD REGISTER 000 PWM OUTPUT ST62T52B ST62T62B/E62B The ARTC counter is initialized by writing to the ARRC register and by then setting the TCLD (Tim- er Load) and the TEN (Timer Clock Enable) bits in the Mode Control register, ARMC. Enabling and selection of the clock source is con- trolled by the CC0, CC1, SL0 and SL1 bits in the Status Control Register, ARSC1 ...

  • Page 42

    ... ST62T52B ST62T62B/E62B AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation. In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit capture operation from the counter to the ARRC register is performed on every active edge on the ARTIMin pin, when enabled by Edge Con- trol bits SL0, SL1 in the ARSC1 register ...

  • Page 43

    ... The flag is cleared by writing a zero to the CPF bit. Bit 0 = OVF: Overflow Interrupt Flag. This bit is set by a transition of the counter from FFh to 00h (overflow). The flag is cleared by writing a zero to the OVF bit. ST62T52B ST62T62B/E62B ARMC0 Operating Mode 0 Auto-reload Mode 1 ...

  • Page 44

    ... ST62T52B ST62T62B/E62B AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: D7h — Read/Write 7 PS2 PS1 PS0 D4 SL1 Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler itself is not affected by these bits. The prescaler division ratio is listed in the following table: Table 14 ...

  • Page 45

    ... If PDS=“1”, the A/D is powered and enabled for conversion. This bit must be set at least one instruction before the beginning of the ST62T52B ST62T62B/E62B conversion to allow stabilisation of the A/D con- verter. This action is also needed before entering WAIT mode, since the A/D comparator is not auto- matically disabled in WAIT mode ...

  • Page 46

    ... ST62T52B ST62T62B/E62B A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily loaded output signals during conversion, if high precision is required. Such switching will affect the supply voltages used as analog references. The accuracy of the conversion depends on the ...

  • Page 47

    ... Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant ST62T52B ST62T62B/E62B bits of the opcode with the byte following the op- code. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space ...

  • Page 48

    ... ST62T52B ST62T62B/E62B 5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following par- agraphs describe the different types ...

  • Page 49

    ... X,Y.Indirect Register Pointers, V & W Short Direct RegistersD. Affected # . Immediate data (stored in ROM memory)* . Not Affected rr. Data space register ST62T52B ST62T62B/E62B tent or an immediate value in relation with the ad- dressing mode. In CLR, DEC, INC instructions the operand can be any of the 256 data space ad- dresses ...

  • Page 50

    ... ST62T52B ST62T62B/E62B INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations ...

  • Page 51

    ... JRZ 4 e b7,rr,ee e a,w pcr pcr 1 Indicates Illegal Instructions Cycle 5 Bit Displacement Operand 3 Bit Address 1byte dataspace address Bytes 1 byte immediate data 12 bit address Addressing Mode 8 bit Displacement ST62T52B ST62T62B/E62B LOW 0110 0111 2 JRC a,(x) 0000 1 prc 1 ind INC 2 JRC 4 ...

  • Page 52

    ... ST62T52B ST62T62B/E62B Opcode Map Summary (Continued) LOW 8 9 1000 1001 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 2 JRNZ abc 0010 1 pcr 2 ext 1 2 JRNZ abc 0011 1 pcr 2 ...

  • Page 53

    ... Tj= RthJA Where:TA = Ambient Temperature. I RthJA =Package thermal resistance (junc Pint + Pport. DD Pint =IDD x VDD (chip internal power). Pport =Port power dissipation (determined Parameter , (source) DD (sink) SS ST62T52B ST62T62B/E62B tion-to ambient). by the user). Value Unit -0.3 to 7 0.3 ...

  • Page 54

    ... ST62T52B ST62T62B/E62B 6.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage Oscillator Frequency OSC I Pin Injection Current (positive) INJ+ I Pin Injection Current (negative) V INJ- Notes: 1. Care must be taken in case of negative current injection, where adapted impedance must be respected on analog sources to not affect the A/D conversion ...

  • Page 55

    ... 5.0V 5mA 5.0V +10µ 5.0V +10mA 5.0V +20mA 5.0V -10µ 5.0V -5.0mA =0mA LOAD V =5.0V DD ST62T52B ST62T62B/E62B Value Unit Min. Typ. Max 0 0 0.2 V 0.2 0.1 0.8 V 0.1 0.8 1.3 4.9 V 3.5 40 100 200 150 350 900 0.1 1 -16 - ...

  • Page 56

    ... ST62T52B ST62T62B/E62B 6.4 AC ELECTRICAL CHARACTERISTICS (T = -40 to +125° C unless otherwise specified) A Symbol Parameter t Supply Recovery Time REC Minimum Pulse Width (V T RESET pin WR NMI pin T EEPROM Write Time WEE (2) Endurance EEPROM WRITE/ERASE Cycle Retention EEPROM Data Retention C Input Capacitance IN C Output Capacitance ...

  • Page 57

    ... Clock Frequency CL t Set-up Time SU t Hold Time h 6.8 ARTIMER ELECTRICAL CHARACTERISTICS (T = -40 to +125° C unless otherwise specified) A Symbol Parameter f Input Frequency on ARTIMin Pin IN ST62T52B ST62T62B/E62B Test Conditions Min 3. 4.5V 125 DD Test Conditions Min. Applied on Scl Applied on Sin Applied onSin Value ...

  • Page 58

    ... ST62T52B ST62T62B/E62B 7 GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 27.16-Pin Plastic Dual In Line Package (B), 300-mil Width Figure 28. 16-Pin Plastic Small Outline Package (M), 300-mil Width 58/ inches Dim. Min Typ Max Min Typ Max A 5.08 .200 A1 .508 .020 B .381 .508 .533 .015 .020 .021 B1 ...

  • Page 59

    ... ST62T52BM3 ST62T62BM6 1836 OTP ST62T62BM3 Test Conditions Min. PDIP16 PSO16 EEPROM (Bytes) Temperature Range +70°C - 85° C None - 125° 85° - 125° C ST62T52B ST62T62B/E62B Value Unit Typ. Max. 55 °C/W 75 Package CDIP16W PSO16 PSO16 59/68 59 ...

  • Page 60

    ... ST62T52B ST62T62B/E62B Notes: 60/68 60 ...

  • Page 61

    R A/D CONVERTER, AUTO-RELOAD TIMER AND EEPROM 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125° C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table capability in Program Memory Data ...

  • Page 62

    ... ST62P52B ST62P62B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62P52B and ST62P62B are the Factory Advanced Service Technique ROM (FASTROM) version of ST62T52B and ST62T62B OTP devic- es. They offer the same functionality as OTP devices, selecting as FASTROM options the options de- fined in the programmable option byte of the OTP version ...

  • Page 63

    ST62P52B and ST62P62B FASTROM MICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . . . . ...

  • Page 64

    ST62P52B ST62P62B Notes: 64/68 64 ...

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    R 8-BIT ROM MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, ROM AND EEPROM 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125° C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up Table ...

  • Page 66

    ... GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6252B and ST6262B are mask pro- grammed ROM version of ST62T52B and ST62T62B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 1. Programming wave form ...

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    ST6252B and ST6262B MICROCONTROLLER OPTION LIST Customer . . . . . . . . . . . . . . . . . . . . . . . . . Address . . . . . . . ...

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    ST6252B ST6262B 1.3 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to SGS-THOMSON. 1.3.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask ...