ds4510u-5t-r Maxim Integrated Products, Inc., ds4510u-5t-r Datasheet
ds4510u-5t-r
Related parts for ds4510u-5t-r
ds4510u-5t-r Summary of contents
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... Four Programmable, NV, Digital I/O Pins with Selectable Internal Pullup Resistor ♦ 64 Bytes of User EEPROM ♦ Reduces Need for Discrete Components ♦ C-Compatible Serial Interface ♦ 10-Pin µSOP Package Applications PART DS4510U-5 DS4510U-10 DS4510U-15 DS4510U-5/T&R DS4510U-10/T&R DS4510U-15/T&R 10 RST 9 I I/O 1 FROM SYSTEM 7 I/O ...
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... Storage Temperature Range .............................-55°C to +125°C Relative Soldering Temperature .......................................See IPC/JEDEC 3 CONDITIONS V (Notes (Note CONDITIONS DS4510U-5 DS4510U-10 CCTP DS4510U- 5.0V (Note 3) STBY 3mA sink current V OL 6mA sink current 4mA sink current OLIOX 10mA sink current (Note 4) OLRST R P ...
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CPU Supervisor with Nonvolatile Memory and CPU SUPERVISOR AC ELECTRICAL CHARACTERISTICS (See (V = 2.7V to 5.5V -40°C to +85°C PARAMETER SYMBOL RST Active Time Detect to RST V CC Fail to RST ...
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CPU Supervisor with Nonvolatile Memory and Programmable I/O NONVOLATILE MEMORY CHARACTERISTICS ( 5.5V 0°C to +70°C.) 2. PARAMETER SYMBOL Writes Note 1: All voltages referenced to ground. Note 2: The DS4510 does not obstruct ...
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CPU Supervisor with Nonvolatile Memory and (V = +5.0V +25°C, unless otherwise noted TRIP POINT vs. TEMPERATURE CC 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 -40 - ...
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CPU Supervisor with Nonvolatile Memory and Programmable I/O SDA 2-WIRE SCL INTERFACE GND EEPROM 64 BYTES USER MEMORY Detailed Description The DS4510 contains a CPU supervisor, four program- mable I/O pins, and a 64-byte EEPROM ...
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CPU Supervisor with Nonvolatile Memory and transistors. Read the I/O status register (F8h) to deter- mine the logic levels present at the I/O pins. Three types of memory are present in the DS4510 (EEPROM, SEEPROM, and SRAM). The main user ...
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CPU Supervisor with Nonvolatile Memory and Programmable I/O REGISTER REGISTER LOCATION NAME Bit 7 (HEX) User 00-3F EE EEPROM Reserved 40-EF n/a Pullup F0 SEE Enable RST Delay F1 SEE User SEE F2 SEE User SEE F3 SEE I/O3 F4 ...
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CPU Supervisor with Nonvolatile Memory and Table 1. Register Definitions REGISTER REGISTER LOCATION (HEX) NAME User EEPROM Reserved F0 Pullup Enable RST Delay User SEEPROM I/O Control ...
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CPU Supervisor with Nonvolatile Memory and Programmable I/O SDA t BUF t LOW SCL t HD:STA STOP START NOTE: TIMING IS REFERENCE TO V AND V IL(MAX) IH(MIN) 2 Figure Timing Diagram address pin allows for the ...
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CPU Supervisor with Nonvolatile Memory and dition, write the slave address (R/W = 0), and the first memory address of the next page before continuing to write data. Acknowledge Polling: Any time an EEPROM page is written, the DS4510 requires ...
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CPU Supervisor with Nonvolatile Memory and Programmable I/O COMMUNICATIONS KEY WHITE BOXES INDICATED THE MASTER IS START ACK S A CONTROLLING SDA NOT SHADED BOXES INDICATED THE SLAVE IS STOP P N ACK CONTROLLING SDA REPEATED ...