ds4550et-r Maxim Integrated Products, Inc., ds4550et-r Datasheet - Page 7

• Manufacturer Part Number: ds4550et-r
• Description: Ds4550 I?c And Jtag Nonvolatile 9-bit I/o Expander Plus Memory
• Manufacturer: Maxim Integrated Products, Inc.

The DS4550 contains nine bidirectional, NV, input/out-
put (I/O) pins, and a 64-byte EEPROM user memory.
The I/O pins and user memory are accessible through
either the I
JTAG interface.
Each programmable I/O pin consists of an input and an
open-collector output with a selectable internal pullup
resistor. To enable the pullups for each I/O pin, write to
the Pullup Enable Registers (F0h and F1h). To pull the
output low or place the pulldown transistor into a high-
SDA
TMS
GND
SCL
TDO
TCK
V
TDI
A1
A2
CC
A0
R
2
JPU
C compatible serial bus or the IEEE 1149.1
V
CC
V
CC
BSC
BSC
BSC
BSC
BSC
R
JPU
Programmable NV I/O Pins
Detailed Description
INTERFACE
CONTROL
64 BYTES
MEMORY
EEPROM
USER
PORT
JTAG
I
2
C
I
2
C and JTAG Nonvolatile 9-Bit I/O
_____________________________________________________________________
PULLUP ENABLE (F0h-F1h)
I/O CONTROL (F2h-F3h)
I/O STATUS (F8h-F9h)
I/O CONTROL
REGISTERS
Expander Plus Memory
impedance state, write to the I/O Control Registers (F2h
and F3h). To read the voltage levels present on the I/O
pins, read the I/O Status Registers (F8h and F9h). To
determine the status of the output register, read the I/O
Control Registers and the Pullup Resistor Registers.
The I/O Control Registers and the Pullup Enable
Registers are all SRAM-shadowed EEPROM registers.
It is possible to disable the EEPROM writes of the regis-
ters using the SEE bit in the Configuration Register.
This reduces the time required to write to the register
and increases the amount of times the I/O pins can be
adjusted before the EEPROM is worn out.
BOUNDARY SCAN CELL (BSC)
I/O CELL
BSC
BSC
BSC
DS4550
V
CC
Block Diagram
R
PU
(x9)
I/O_n
[n = 0 TO 8]
7