ltc4253a-adj Linear Technology Corporation, ltc4253a-adj Datasheet
ltc4253a-adj
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ltc4253a-adj Summary of contents
Page 1
... The LTC4253A-ADJ latches off after a circuit fault. Undervoltage and overvoltage detectors with adjustable thresholds and hystereses disconnect the load whenever the input supply exceeds the desired operating range. The LTC4253A-ADJ’ ...
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... EN2, EN3 Input Current (Note 1) All voltages referred to V Operating Temperature Range LTC4253A-ADJC ..................................... 0°C to 70°C LTC4253A-ADJI .................................. – 40°C to 85°C Storage Temperature Range SSOP ................................................ – 65°C to 150°C QFN .................................................. – 65°C to 125°C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300°C W ...
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... I = 0µA DRN TMR Timer On (Circuit Breaker, Sourcing 50µA DRN TMR Timer Off (Circuit Breaker, Sinking 0µA) Timer On (Circuit Breaker with I = 50µA) DRN LTC4253A-ADJ MIN TYP MAX ● ±0.1 ±10 ● ● ● 105 ...
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... LTC4253A-ADJ ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER I SQTIMER Pin Current SQTMR V DRAIN Pin Voltage Low Threshold DRNL I DRAIN Leakage Current DRNL V DRAIN Pin Clamp Voltage DRNCL V PWRGD1, PWRGD2, PWRGD3 Signals PGL Output Low Voltage I PWRGD1, PWRGD2, PWRGD3 ...
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... UV/UVL/OV/OVL = 4V 14.0 TIMER = 0V 13 SENSE EE 13.0 12.5 12.0 11.5 11.0 10.5 10.0 –50 – 100 125 TEMPERATURE (°C) 4253A G11 LTC4253A-ADJ Analog Current Limit Voltage V ACL vs Temperature 2mA –50 – 100 125 TEMPERATURE (°C) 4253A G06 I (ACL, Sink) vs Temperature ...
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... LTC4253A-ADJ W U TYPICAL PERFOR A CE CHARACTERISTICS V vs Temperature GATEH 3 2mA UV/UVL/OV/OVL = 4V 3 – V GATEH IN GATE 3.2 3.0 2.8 2.6 2.4 2.2 2.0 –50 – 100 125 TEMPERATURE (°C) 4253A G13 – SENSE SENSE EE 0.01 0 2mA IN UV/UVL/OV/OVL = 4V 100 TIMER = 0V GATE = HIGH T = 25°C ...
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... IN 190 SS PIN FLOATING V RAMPS FROM 0.2V TO 1.25V SS 180 170 160 150 140 130 120 110 100 – 100 –25 TEMPERATURE (°C) 4253A G29 LTC4253A-ADJ V vs Temperature DRNL 2. 2mA 2.55 2.50 2.45 2.40 2.35 2.30 2.25 2.20 125 –50 – TEMPERATURE (° Temperature PGL 2 ...
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... LTC4253A-ADJ CTIO S (SSOP/QFN) EN2 (Pin 1/Pin 18): Power Good Status Output Two Enable. This is a TTL compatible input that is used to control PWRGD2 and PWRGD3 outputs. When EN2 is driven low, both PWRGD2 and PWRGD3 will go high. When EN2 is driven high, PWRGD2 will go low provided ...
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... PWRGD2 goes low, whichever comes under all circum- UV later. PWRGD3 is reset by PWRGD1 going high or EN3 going low. This pin is internally pulled high by a 50µA current source. LTC4253A-ADJ for the power good SQT ). EN3 can be SQT . PWRGD3 will ...
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... LTC4253A-ADJ W BLOCK DIAGRA 50µA PWRGD1 SQTIMER DELAY V EE EN2 V IN 120µA 50µ PWRGD2 SQTIMER V EE EN3 V IN 120µA 50µ PWRGD3 SQTIMER V EE OVL 5.09V OVIN OV UVIN UVL UV 3.08V 200µA 5µA TIMER 5µA ...
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... The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4253A-ADJ is designed to turn on a circuit board supply in a controlled manner, allowing insertion or re- moval without glitches or connector damage. ...
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... If, due to an output overload, the voltage drop across R DRNL exceeds 50mV, TIMER sources 200µA into C ally charges threshold and the LTC4253A-ADJ shuts off. If the overload goes away before C and SENSE measures less than 50mV, C charges (5µA). In this way the LTC4253A-ADJ’s circuit ...
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... As before, TIMER runs and shuts down LTC4253A-ADJ when C reaches 4V reaches 4V, the LTC4253A-ADJ latches off with a 5µA T pull-up current source. The LTC4253A-ADJ circuit breaker latch is reset by either pulling the RESET pin active high for >20µs, pulling UVL/UV momentarily low, dropping the ...
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... LTC4253A-ADJ U U APPLICATIO S I FOR ATIO SHUNT REGULATOR A fast responding regulator shunts the LTC4253A-ADJ V pin. Power is derived from –48RTN by an external current limiting resistor. The shunt regulator clamps 1µF decoupling capacitor transients and contributes a short delay at start-up. R should be chosen to accommodate both V rent and the drive required for three optocouplers used by the PWRGD signals ...
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... The divider values shown set a standing current of slightly more than 150µA and define an impedance at UVL/UV/ OVL/OV of approximately 20k. This impedance will work with the hysteresis set across UVL/UV and OVL/OV to provide noise immunity to the UV and OV comparators. If LTC4253A-ADJ OVHI V ...
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... I and effectively short- above V DRNCL charging of C Intermittent overloads may exceed the 50mV threshold at SENSE but, if their duration is sufficiently short, TIMER will not reach 4V and the LTC4253A-ADJ will not shut the is used fast charge; circuit breaker delay. DRN • T µ ...
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... V < 5V and an aggregate duty cycle OUT of more than 2.5% will eventually trip the circuit breaker and shut down the LTC4253A-ADJ. Figure 3 shows the circuit breaker response time in seconds normalized to 1µF. The asymmetric charging and discharging of C fair gauge of MOSFET heating. ...
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... SS OS resultant inrush current profile presents a smooth ramp up from zero (Figure 4b). If there is little inrush current so the LTC4253A-ADJ does not enter current limit masked off when DRAIN goes below 2.39V (V latched off when GATE goes within 2. minimum C of 5nF is required for the stability of the ...
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... Figure 5 trace 1, can rob charge from output capacitors on the adjacent card. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4253A-ADJs are used by the other cards, they respond by limiting the inrush current to a value of V ...
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... MAX ( ) where V = 45mV represents the guaranteed mini- CB(MIN) mum circuit breaker threshold. During the initial charging process, the LTC4253A-ADJ may operate the MOSFET in current limit, forcing (V between 54mV to 66mV across R S current is given by: V ACL MIN ( ) = I INRUSH MIN ...
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... ADJ’ 33nF. SS The drawing in Figure 7 illustrates the correct way of making connections between the LTC4253A-ADJ and the sense resistor. PCB layout should be balanced and sym- metrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal (10Ω) ...
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... LTC4253A-ADJ U U APPLICATIO S I FOR ATIO TIMING WAVEFORMS System Power-Up Figure 8 details the timing waveforms for a typical power- up sequence in the case where a board is already installed in the backplane and system power is applied abruptly CLEARS V IN LKO 1 2 GND – (–48RTN) – (–48V) ...
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... UV/OV divider makes contact through a short pin. This ensures the power con- threshold is TMRL nections are firmly established before the LTC4253A-ADJ , SENSE < V GATEL CB is activated. At time point 1, the power pins make contact and V ...
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... W U Undervoltage Timing In Figure 10 when the UVL pin drops below V point 1), the LTC4253A-ADJ shuts down with TIMER, SS and GATE pulled low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. . When UV recovers and clears V initial time cycle begins followed by a start-up cycle. ...
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... V to start LKO disconnects. At time point 2, OVL recovers and drops below the V overvoltage glitch is long enough to deplete the load capacitor, time points 4 through 7 may occur. LTC4253A-ADJ , SENSE < < 20 • V AND TIMER < TMRL , CHECK GATE < SENSE < V AND SS < ...
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... LTC4253A-ADJ latches TIMER high with a 5µA pull-up current source. Resetting a Fault Latch A latched circuit breaker fault of the LTC4253A-ADJ has the benefit of a long cooling time. The latched fault can be reset by pulsing the RESET pin high for >20µs to over- come the internal glitch filter as shown in Figure 13b. ...
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... At time point 6, the GATE voltage is ACL controlled by the current limit amplifier. The soft-start control voltage reaches the circuit breaker voltage, V time point 7 and the circuit breaker TIMER activates. As the load capacitor nears full charge, load current begins LTC4253A-ADJ CB TIMES-OUT ...
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... LTC4253A-ADJ U U APPLICATIO S I FOR ATIO 4253a-adjf ...
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... MOSFET’s threshold and inrush current starts to flow. At time point connected SS servo released while the GATE voltage is con- trolled by the current limit amplifier with V up from near zero. The result is a current profile (as LTC4253A-ADJ CB TIMES-OUT 2 V FCL V ACL ...
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... A soft-start voltage below V activate the circuit breaker TIMER. Power Limit Circuit Breaker Figure 16 shows the LTC4253A-ADJ in a power limit circuit breaking application. The SENSE pin is modulated by board voltage V . The zener voltage, V SUPPLY ...
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... INCHES (MILLIMETERS) UF Package 20-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1710) 4.00 ± 0.10 (4 SIDES) 0.70 ±0.05 PIN 1 TOP MARK (NOTE 6) PACKAGE OUTLINE LTC4253A-ADJ .337 – .344* (8.560 – 8.738) .058 (1.473 REF .150 – .157** (3.810 – 3.988) ...
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... LTC4253A-ADJ U U APPLICATIO S I FOR ATIO Circuit Breaker with Foldback Current Limit Figure 17 shows the LTC4253A-ADJ in a foldback current limit application. When V is shorted to the – 48V RTN OUT supply, current flows through resistors R4 and R5. This results in a voltage drop across R5 and a corresponding ...