ltc4253a-adj Linear Technology Corporation, ltc4253a-adj Datasheet - Page 16

• Manufacturer Part Number: ltc4253a-adj
• Description: 48v Hot Swap Controller With Sequencer
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
LTC4253A-ADJ
more noise immunity is desired, add a 1nF to 10nF filter
capacitor from UVL to V
UV/OV OPERATION
An undervoltage condition detected by the UV comparator
immediately shuts down the LTC4253A-ADJ, pulls GATE,
SS and TIMER low and resets the three latched PWRGD
signals high. Recovery from an undervoltage will initiate
an initial timing sequence if the other interlock conditions
are met.
An overvoltage condition is detected by the OV compara-
tor and pulls GATE low, thereby shutting down the load,
but it will not reset the circuit breaker TIMER and PWRGD
flags. Returning from the overvoltage condition will
restart the GATE pin if all the interlock conditions except
TIMER are met. Only during the initial timing cycle does an
overvoltage condition have an effect of resetting TIMER.
The internal UVLO at V
or undervoltage.
DRAIN
Connecting an external resistor, R
DRAIN pin allows V
drop) sensing without it being damaged by large voltage
transients. Below 5V, negligible pin leakage allows a
DRAIN low comparator to detect V
(V
starts the power good sequencing.
When V
and the current flowing in R
This current is scaled up 8 times during a circuit breaker
fault before being added to the nominal 200µA. This
accelerates the fault TIMER pull-up when the MOSFET’s
drain-source voltage exceeds V
ens the MOSFET heating duration.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor C
16
DRNL
I
DRN
). This, together with the GATE low comparator,
OUT
≈
V
> V
OUT
DRNCL
−
R
D
V
U
DRNCL
OUT
, the DRAIN pin is clamped at V
IN
EE
always overrides an overvoltage
(MOSFET drain-source voltage
U
.
D
is given by:
DRNCL
D
, to this dual function
W
OUT
and effectively short-
less than 2.39V
T
U
is used at
DRNCL
(2)
TIMER to provide timing for the LTC4253A-ADJ. Four
different charging and discharging modes are available at
TIMER:
1. 5µA slow charge; initial timing delay.
2. (200µA + 8 • I
3. 5µA slow discharge; circuit breaker “cool-off.”
4. Low impedance switch; resets the TIMER capacitor
For initial timing delay, the 5µA pull-up is used. The low
impedance switch is turned off and the 5µA current source
is enabled when the interlock conditions are met. C
charges to 4V in a time period given by:
When C
turns on and discharges C
and both SS and GATE outputs are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than 50mV drop across
R
C
LTC4253A-ADJ latches off. The LTC4253A-ADJ remains
latched off until the RESET pin is momentarily pulsed
high, the UVL/UV pin is momentarily pulsed low, the
TIMER pin is momentarily discharged low by an external
switch or V
circuit breaker timeout period is given by:
If V
current and this makes I
above V
charging of C
Intermittent overloads may exceed the 50mV threshold at
SENSE but, if their duration is sufficiently short, TIMER
will not reach 4V and the LTC4253A-ADJ will not shut the
T
S
after an initial timing delay, in UVLO, in UV and in OV
during initial timing and when RESET is high.
, the TIMER pin charges C
t
t
OUT
charges to 4V, the GATE pin pulls low and the
=
=
4
200
< 5V, an internal PMOS isolates DRAIN pin leakage
T
V C
DRNCL
5
reaches V
µ
•
µ +
IN
A
4
A
V C
T
T
dips below UVLO and is then restored. The
during the circuit breaker fault period, the
•
is accelerated by 8 • I
8
DRN
T
•
I
TMRH
DRN
) fast charge; circuit breaker delay.
DRN
(4V), the low impedance switch
T
. A GATE start-up cycle begins
T
= 0 in Equation 4. If V
with (200µA + 8 • I
DRN
of Equation 2.
DRN
4253a-adjf
OUT
). If
(3)
(4)
is
T