ltc6993-1 Linear Technology Corporation, ltc6993-1 Datasheet - Page 12

• Manufacturer Part Number: ltc6993-1
• Description: Electrical Specifications Subject To Change
• Manufacturer: Linear Technology Corporation

operaTion
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
The LTC6993 is built around a master oscillator with a 1µs
minimum period. The oscillator is controlled by the SET
pin current (I
conversion factor that is accurate to ±1.7% under typical
conditions.
A feedback loop maintains V
I
The simplest way to generate I
(R
The master oscillator equation reduces to:
From this equation, it is clear that V
the pulse width when using a single program resistor
(R
inherent pulse width accuracy ∆t
R
between 1.25µA and 20µA).
A trigger signal (rising or falling edge on TRIG pin) latches
the output to the active state, beginning the output pulse.
At the same time, the master oscillator is enabled to time
the duration of the output pulse. When the desired pulse
width is reached, the master oscillator resets the output
latch.
The LTC6993 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
512, 4096, 2
duration by those same factors. The divider ratio N
set by a resistor divider attached to the DIV pin.
With R

SET
SET
SET
SET
t
t
t
t
MASTER
MASTER
OUT
OUT
as the primary means of controlling the pulse width.
) between SET and GND, such that I
). Error sources are limited to R
may range from 50k to 800k (equivalent to I
SET
=
=
N
50
in place of V
N
DIV
=
= 1
DIV
15
k
50
SET
50 Ω
Ω
µs
, 2
1
•
k
µs
k
R
•
) and voltage (V
Ω
18
•
SET
V
I
50
SET
R
SET
or 2
•
SET
k
V
I
•
SET
Ω
SET
SET
1
•
21
µs
1
µs
. This extends the pulse width
/I
SET
SET
SET
the equation reduces to:
OUT
SET
is to connect a resistor
at 1V ±30mV, leaving
SET
SET
), with a 1µs/50kΩ
of the LTC6993.
drift will not affect
tolerance and the
SET
= V
SET
/R
DIV
SET
SET
is
.
DIVCODE
The DIV pin connects to an internal, V
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6993:
1. DIVCODE determines the frequency divider setting,
2. DIVCODE determines the polarity of OUT pin, via the
V
and GND as shown in Figure 1.
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding N
resistor pairs. Other values may be used as long as:
1. The V
2. The driving impedance (R1||R2) does not exceed
If the voltage is generated by other means (i.e., the output
of a DAC) it must track the V
column in Table 1 shows the ideal ratio of V
supply voltage, which can also be calculated as:
For example, if the supply is 3.3V and the desired DIVCODE
is 4, V
Figure 2 illustrates the information in Table 1, showing that
N
DIV
DIV
N
POL bit.
tor tolerances and temperature effects).
500kΩ.
V
V
DIV
DIV
may be generated by a resistor divider between V
is symmetric around the DIVCODE midpoint.
+
DIV
.
Figure 1. Simple Technique for Setting DIVCODE
DIV
=
= 0.281 • 3.3V = 928mV ± 50mV.
DIVCODE
/V
+
ratio is accurate to ±1.5% (including resis-
DIV
16
and POL values for the recommended
LTC6993
+
0 5
69931234 F01
.
GND
DIV
V
±
+
1 5
2.25V TO 5.5V
. %
+
supply voltage. The last
R1
R2
+
referenced 4-bit A/D
DIV
69931234p
to the
+