ltc6803g-3 Linear Technology Corporation, ltc6803g-3 Datasheet - Page 18

• Manufacturer Part Number: ltc6803g-3
• Description: Ltc6803-1/ltc6803-3 - Multicell Battery Stack Monitor
• Manufacturer: Linear Technology Corporation

LTC6803-1/LTC6803-3
OPERATION
An example to calculate the PEC is listed in Table 1 and
Figure 5. The PEC of the 1 byte data 0x01 is computed as
0xC7 after the last bit of the byte clocked in. For multiple
byte data, the PEC is valid at the end (LSB) of the last byte.
LTC6803 calculates PEC byte for any command or data
received and compares it with the PEC byte following the
command or data. The command or data is regarded as
valid only if the PEC bytes match. LTC6803 also attaches
the calculated PEC byte at the end of the data it shifts out.
For daisy-chained LTC6803-1/LTC6803-3, each device
computes the PEC byte based on the data it sends out
or receives for itself. The data passing through for other
devices do affect its PEC. On a read command, each device
shifts its data out with, and then shifts out the PEC byte it
computed, MSB first. For example, when reading the flag
registers from two stacked devices (bottom device A and
top device B), the data will be output in the following order:
On a write command, each device receives its data and
then the PEC byte, MSB first. For example, when writing
configuration registers to two stacked devices (bottom
device A and top device B), the data will be input in the
following order:
Broadcast Commands: A broadcast command is one to
which all devices on the bus will respond, regardless of
Table 1. Procedure to Calculate PEC Byte
18
CLOCK
CYCLE
FLGR0(A), FLGR1(A), FLGR2(A), PEC(A), FLGR0(B),
FLGR1(B), FLGR2(B), PEC(B )
CFGRR0(B), CFGR1(B),……, CFGR5(B), PEC(B),
CFGR0(A), CFGR1(A),……, CFGR5(A), PEC(A)
0
1
2
3
4
5
6
7
8
DIN
0
0
0
0
0
0
0
1
IN0
0
1
0
0
0
0
0
1
IN1
1
1
1
0
0
0
0
1
IN2
0
0
1
1
0
0
0
1
PEC[7]
0
1
0
0
0
0
0
0
1
PEC[6]
1
0
0
0
0
0
0
1
1
device address. See the Bus Protocols and Commands
sections.
In daisy-chained configurations, all devices in the chain
receive the command bytes simultaneously. For example,
to initiate ADC conversions in a stack of devices, a single
STCVAD command is sent, and all devices will start con-
versions at the same time. For read and write commands,
a single command is sent, and then the stacked devices
effectively turn into a cascaded shift register, in which
data is shifted through each device to the next higher (on
a write) or the next lower (on a read) device in the stack.
See the Serial Command Examples section.
Polling Methods: For ADC conversions, three methods can
be used to determine ADC completion. First, a controller
can start an ADC conversion and wait for the specified
conversion time to pass before reading the results. The
second method is to hold CSBI low after an ADC start
command has been sent. The ADC conversion status will
be output on SDO (Figure 6). A problem with the second
method is that the controller is not free to do other serial
communication while waiting for ADC conversions to
complete. The third method overcomes this limitation.
The controller can send an ADC start command, perform
other tasks, and then send a poll ADC converter status
(PLADC) command to determine the status of the ADC
conversions (Figure 7). For OV/UV interrupt status, the poll
interrupt status (PLINT) command can be used to quickly
determine whether any cell in a stack is in an overvoltage
or undervoltage condition (Figure 7).
PEC[5]
0
0
0
0
1
1
0
0
0
PEC[4]
0
0
0
0
0
1
1
0
0
PEC[3]
0
0
0
0
1
1
0
0
0
PEC[2]
0
0
0
1
1
0
0
0
1
PEC[1]
0
1
1
1
0
0
0
0
1
PEC[0]
1
0
1
0
0
0
0
0
1
680313f