nt1gt72u4pa0bv Nanya Techology, nt1gt72u4pa0bv Datasheet - Page 12

• Manufacturer Part Number: nt1gt72u4pa0bv
• Description: 240pin Registered Ddr2 Sdram Module Based On 64mx8 & 128mx4 Ddr2 Sdram Die A
• Manufacturer: Nanya Techology

NT512T72U89A0BV / NT1GT72U4PA0BV / NT2GT72U4NA2BV
512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72
Registered DDR2 SDRAM DIMM
Serial Presence Detect --
256Mx72 2 RANKS REGISTERED DDR2 SDRAM DIMM based on 128Mx4, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD
REV 1.2
09/2006
Byte
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
0
1
2
3
4
5
6
7
8
9
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Reserved
Voltage Interface Level of this Assembly
DDR2 SDRAM Device Cycle Time at CL=5
DDR2 SDRAM Device Access Time from Clock at CL=5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR2 SDRAM Width
Error Checking DDR2 SDRAM Device Width
Reserved
DDR2 SDRAM Device Attributes: Burst Length Supported
DDR2 SDRAM Device Attributes: Number of Device Banks
DDR2 SDRAM Device Attributes: CAS Latencies Supported
DIMM Mechanical Characteristics
DDR2 SDRAM DIMM Type Information
DDR2 SDRAM Module Attributes:
DDR2 SDRAM Device Attributes: General
Minimum Clock Cycle at CL=5
Maximum Data Access Time from Clock at CL=5
Minimum Clock Cycle Time at CL=3
Maximum Data Access Time from Clock at CL=3
Minimum Row Precharge Time (t
Minimum Row Active to Row Active delay (t
Minimum RAS to CAS delay (t
Minimum RAS Pulse Width (t
Module Bank Density
Address and Command Setup Time Before Clock (tIS)
Address and Command Hold Time After Clock (tIH)
Data Input Setup Time Before Clock (tDS)
Data Input Hold Time After Clock (tDH)
Write Recovery Time (tWR)
Internal Write to Read Command delay (tWTR)
Internal Read to Precharge delay (tRTP)
Reserved
Extension of Byte 41 tRC and Byte 42 tRFC
Minimum Core Cycle Time (tRC)
Description
RAS
Part 1 of 2 (2GB)
RCD
)
RP
)
)
RRD
)
12
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
t
RFC
decimal point of t
2 rank, Height=30mm
The number below a
Support weak driver
are 0, t
SPD Entry Value
DDR2-SDRAM
Normal DIMM
Reg. DIMM
DDR2-667
Undefined
Undefined
Undefined
SSTL_1.8
7.8µs/SR
<4.10mm
±0.45ns
0.175ns
3.75ns
±0.5ns
±0.6ns
0.27ns
256ns
parity
7.5ns
0.2ns
0.1ns
7.5ns
7.5ns
3/4/5
15ns
15ns
45ns
15ns
60ns
1GB
X72
RFC
-3C
128
256
3ns
5ns
4,8
X4
X4
14
11
4
is less than
RC
and
Serial PD Data Entry
(Hexadecimal)
DDR2-667
© NANYA TECHNOLOGY CORP.
-3C
0C
3D
3C
3C
2D
3C
3C
80
08
08
0E
0B
61
48
00
05
30
45
06
82
04
04
00
04
38
01
01
00
03
50
50
60
1E
01
20
27
10
17
1E
1E
00
00
Note