rm5261a pmc-sierra, rm5261a Datasheet
rm5261a
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rm5261a Summary of contents
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... RM5261A™ Microprocessor with 64-Bit Proprietary and Confidential Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet RM5261A System Bus Data Sheet Released Issue 4, February 2004 ...
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... Fax: +1 (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Released 2 ...
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... All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold typeface. All instruction names, such as MFHI, are in san serif typeface. • Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Released 4 ...
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... Handshake Signals ......................................................................................................22 3.25 Non-overlapping System Interface ...............................................................................23 3.26 Enhanced Write Modes ................................................................................................24 3.27 External Requests ........................................................................................................24 3.28 Interrupt Handling ........................................................................................................25 3.29 Standby Mode ..............................................................................................................25 3.30 JTAG Interface .............................................................................................................25 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Released 5 ...
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... Packaging Information .........................................................................................................37 12. RM5261A 208-QFP Package Numerical Pinout ..................................................................38 13. RM5261A 208-QFP Package Alphabetical Pinout ..............................................................40 14. Ordering Information ............................................................................................................42 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Released 6 ...
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... Figure 7 Processor Block Read ............................................................................................................23 Figure 8 Processor Block Write .................................................................................................24 Figure 9 Clock Timing ................................................................................................................36 Figure 10 Input Timing ...............................................................................................................36 Figure 11 Output Timing ............................................................................................................36 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Released 7 ...
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... Table 5 System Interface ...........................................................................................................27 Table 6 Clock/Control Interface .................................................................................................28 Table 7 Interrupt Interface .........................................................................................................28 Table 8 JTAG Interface .............................................................................................................28 Table 9 Initialization Interface ....................................................................................................29 Table 10 Power Supply .............................................................................................................29 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Released 8 ...
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... Standby reduced power mode with WAIT instruction • 1. 1.8 V core with 3 2.5 V I/O • 208-pin QFP package Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Released 9 ...
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... Register File Packer/Unpacker Floating-Point MultAdd, Add, Sub, Cvt, Div, Sqrt Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet DTag ITag DTLB ITLB Pad Buffer Address Buffer ...
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... The key elements of the RM5261A are briefly described below. 3.1 Superscalar Dispatch The RM5261A has an asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. Integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, and convert ...
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... In addition to the integer pipeline, the RM5261A implements an extended 7-stage pipeline for floating-point operations. The RM5261A multiplies the input pipeline clock. Figure 3 shows the RM5261A integer pipeline. As illustrated in the figure five integer instructions can be executing simultaneously. Figure 3 Pipeline I0 ...
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... Hi and Lo registers. These values can then be transferred to the general purpose register file using the Move-from-Hi and Move-from-Lo ( MFHI / MFLO ) instructions. In addition to the baseline MIPS IV integer multiply instructions, the RM5261A also implements the 3-operand multiply instruction, MUL . This instruction specifies that the multiply result go directly to the integer register file rather than the Lo register ...
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... Overlap of the divide/square root and multiply/add operations is supported. The RM5261A maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. Precise exceptions are extremely important in object-oriented programming environments and highly desirable for debugging in any environment. ...
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... JTLB, and co-processor registers used by the virtual memory mapping sub-system. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Repeat Rate 1 1 ...
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... This mechanism allows system software to provide a secure environment for user processes. Bits in the CP0 register Status determine which virtual addressing mode is used. In the user mode, the RM5261A provides a single, uniform virtual address space 32-bit mode). When operating in the kernel mode, four distinct virtual address spaces, totalling over 2 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address ...
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... The RM5261A processors also support a supervisor mode in which the virtual address space over 32-bit mode), divided into three regions based on the high-order bits of the virtual address. When the RM5261A is configured as a 64-bit microprocessor, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout. ...
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... TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The RM5261A provides a random replacement algorithm to select a TLB entry to be written with a new mapping; however, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism uses the Wired register and allows the operating system to guarantee that certain pages are always mapped for performance reasons and for deadlock avoidance ...
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... Data Cache For fast, single cycle data access, the RM5261A includes on-chip data cache that is two- way set associative with a fixed 32-byte (eight words) line size. The data cache is protected with byte parity and its tag is protected with a single parity bit virtually indexed and physically tagged to allow simultaneous address translation and data cache access ...
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... If the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). The store buffer allows the RM5261A to execute a store every processor cycle and to perform back-to-back stores without penalty. In the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred ...
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... GB/sec with a 125 MHz SysClock. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Instruction Data 32KB ...
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... Handshake Signals There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an external device to indicate to the RM5261A whether it can accept a new read or write Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ ...
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... RM5261A issues another request. The RM5261A can issue read and write requests to an external device, whereas an external device can issue null and write requests to the RM5261A. For processor reads the RM5261A asserts ValidOut* and simultaneously drives the address and read command on the SysAD and SysCmd buses respectively ...
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... RM5261A. An independent transfer is a data transfer between two external agents or between an external agent and memory or peripheral on the system interface. Following the asserting of the ExtRqst*, the RM5261A tri-states its drivers allowing the external agent to use the system interface buses to complete an independent transfer. The external agent is responsible for returning mastership of the system interface to the RM5261A when it has completed the independent transfer and does so by executing an External Null cycle ...
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... Standby Mode The RM5261A provides a means to reduce the amount of power consumed by the internal core when the CPU is not performing any useful operations. This state is known as Standby Mode. Executing the WAIT instruction enables interrupts and causes the processor to enter Standby Mode ...
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... Output driver strength - 100% = fastest 00: 67% strength 01: 50% strength 10: 100% strength 11: 83% strength Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Mode bit 15 17:16 19:18 Mode Bit 20=0 ...
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... Pin Descriptions The following is a list of interface, interrupt, and miscellaneous pins available on the RM5261A. An asterisk (*) at the end of the the signal name denotes active-low. Table 5 System Interface Pin Name Type ExtRqst* Input Release* Output RdRdy* Input WrRdy* Input ValidIn* Input ValidOut* Output ...
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... JTMS Input Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Description System Clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization ...
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... ROM When asserted, this signal indicates to the RM5261A that both power supplies has been above the recommended value for more than 100 milliseconds and will remain stable. The assertion of V the reading of the boot-time mode control serial stream. ...
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... Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet 1 SS should not exceed 3.9 Volts. ...
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... CC passive filter circuit. See the RM5200 User’s Manual for the recommended filter circuit. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Case Temperature V V Int ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Minimum Maximum 0.2 V VccIO - 0.2 V 0.4 V 2.4 V -0.3 V 0.8 V 2.0 V VccIO + 0 Minimum Maximum ...
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... IO supply power is application dependant, but typically <20 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet CPU Speed 250 MHz 300 MHz 350 MHz 400 MHz 1 ...
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... JTAG Clock t JTAGCKP Period Notes: 1. Operation of the RM5261A is only guaranteed with the Phase Lock Loop Enabled. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Symbol Min C — ...
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... Symbol Mode Data Setup t DS Mode Data Hold t DH Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet 1 CPU Speed 250 to 350 MHz Min Max 5,6 1.0 5.0 (fastest) 5,6 1 ...
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... System Interface Timing Figure 10 Input Timing SysClock Data Figure 11 Output Timing SysClock Data Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet t t High Low t t Fall Rise (SysAD, SysCmd, ValidIn*, ValidOut*, etc ...
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... Pin numbers start with pin 1 and continue counter-clockwise to pin 208 when viewed from the top. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet 0.20 (0.008 A–B ...
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... SysAD10 68 27 SysAD42 69 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Function Pin Function Pin SysAD47 85 SysCmd8 127 SysCmdP 128 CC ...
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... SysAD46 Int SysAD15 84 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Function Pin Function Pin V 112 V IO 154 Int 113 V ...
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... SysAD27 NC 154 SysAD28 NC 155 SysAD29 NC 157 SysAD30 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Pin Function Pin Function 6 SysAD46 39 V Int CC 8 SysAD47 ...
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... SysAD1 193 SysAD43 SysAD2 197 SysAD44 SysAD3 199 SysAD45 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Pin Function Pin Function 173 SysCmd0 ...
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... RM5261A–300–HI (contact sales prior to design) RM5261A–350–H RM5261A–400–H Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002240, Issue 4 RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet Temperature Grade: (blank) = commercial I = Industrial Package Type: ...