rm5261a pmc-sierra, rm5261a Datasheet - Page 18

• Manufacturer Part Number: rm5261a
• Description: Rm5261a Tm Microprocessor With 64-bit System Bus
• Manufacturer: pmc-sierra

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 4
3.17 Cache Memory
3.18 Instruction Cache
3.19 Data Cache
The RM5261A incorporates on-chip instruction and data caches that can be accessed in a single
processor cycle. Each cache has its own 64-bit data path and both caches can be accessed
simultaneously. The cache subsystem provides the integer and floating-point units with an
aggregate bandwidth of 3.2 GB per second at an internal clock frequency of 200 MHz.
The RM5261A incorporates a two-way set associative on-chip instruction cache. This virtually
indexed, physically tagged cache is 32 KB in size and is protected with word parity.
Since the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel
with the cache access, further increasing performance by allowing these two operations to occur
simultaneously. The cache tag contains a 24-bit physical address, a valid bit, and a single parity bit.
The instruction cache is 64-bits wide and can be accessed each processor cycle. Accessing 64 bits
per cycle allows the instruction cache to supply two instructions per cycle to the superscalar
dispatch unit. For typical code sequences where a floating-point load or store and a floating-point
computation instruction are being issued together in a loop, the entire bandwidth available from
the instruction cache is consumed.
Cache miss refill writes 64 bits per cycle to minimize the cache miss penalty. The line size is eight
instructions (32 bytes) to maximize the performance of communication between the processor and
the memory system.
The RM5261A supports cache locking. The contents of set A of the cache can be locked by setting
a bit in the coprocessor 0 Status register. Locking the set prevents its contents from being
overwritten by a subsequent cache miss. Refills occur only into set B. This mechanism allows the
programmer to lock critical code into the cache, thereby guaranteeing deterministic behavior for
the locked code sequence.
For fast, single cycle data access, the RM5261A includes a 32 KB on-chip data cache that is two-
way set associative with a fixed 32-byte (eight words) line size.
The data cache is protected with byte parity and its tag is protected with a single parity bit. It is
virtually indexed and physically tagged to allow simultaneous address translation and data cache
access.
Cache protocols supported for the data cache are:
1. Uncached
2. Write-back
Data loads and instruction fetches from uncached memory space are brought in from the main
memory to the register file and the execution unit, respectfully. The caches are not accessed.
Data stores to uncached memory space go directly to the main memory without updating the
data cache.
Loads and instruction fetches first search the cache, reading main memory only if the desired
data is not cache resident. On data store operations, the cache is first searched to determine if
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Released
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