ad73422 Analog Devices, Inc., ad73422 Datasheet - Page 20

• Manufacturer Part Number: ad73422
• Description: Dual Low Power Cmos Analog Front End With Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

AD73422
A description of a single device operating in mixed mode is
detailed in Appendix B, while Appendix D details the initializa-
tion and operation of a dual codec cascade operating in mixed
mode. Note that it is not essential to load the control registers in
Program Mode before setting mixed mode active. It is also
possible to initiate mixed mode by programming CRA with the
first control word and then interleaving control words with
DAC data.
Digital Loop-Back
This mode can be used for diagnostic purposes and allows the
user to feed the ADC samples from the ADC register directly to
the DAC register. This forms a loop-back of the analog input to
the analog output by reconstructing the encoded signal using
the decoder channel. The serial interface will continue to work,
which allows the user to control gain settings, etc. Only when
DLB is enabled with mixed mode operation can the user disable
the DLB, otherwise the device must be reset.
SPORT Loop-Back
This mode allows the user to verify the DSP interfacing and
connection by writing words to the SPORT of the devices and
have them returned back unchanged after a delay of 16 SCLK
cycles. The frame sync and data words that are sent to the de-
vice are returned via the output port. Again, SLB mode can only
be disabled when used in conjunction with mixed mode, other-
wise the device must be reset.
Analog Loop-Back
In Analog Loop-Back mode, the differential DAC output is
connected, via a loop-back switch, to the ADC input. This
mode allows the ADC channel to check functionality of the
DAC channel as the reconstructed output signal can be moni-
tored using the ADC as a sampler. Analog Loop-Back is en-
abled by setting the ALB bit (CRF:7)
NOTE: Analog Loop-Back can only be enabled if the Analog
Gain Tap is powered down (CRC:1 = 0).
AFE Interfacing
The AFE section SPORT (SPORT2) can be interfaced to either
SPORT0 or SPORT1 of the DSP section. Both serial input and
output data use an accompanying frame synchronization signal
VOUTN1
REFOUT
REFCAP
VOUTP1
VFBN1
VFBP1
VINN1
VINP1
INVERTING
Figure 9. Analog Loop-Back Connectivity
OP AMPS
V
REF
LOOP-BACK
ANALOG
SELECT
+6/–15dB
REFERENCE
PGA
GAIN
1
CONTINUOUS
LOW-PASS
INVERT
FILTER
TIME
AFE SECTION
AD73422
ANALOG GAIN TAP
POWERED DOWN
SINGLE-ENDED
ENABLE
V
REF
0/38dB
PGA
–20–
which is active high one clock cycle before the start of the 16-bit
word or during the last bit of the previous word if transmission
is continuous. The serial clock (SCLK) is an output from the
codec and is used to define the serial transfer rate to the DSP’s
Tx and Rx ports. Two primary configurations can be used: the
first is shown in Figure 10 where the DSP’s Tx data, Tx frame
sync, Rx data and Rx frame sync are connected to the codec’s
SDI, SDIFS, SDO and SDOFS respectively. This configura-
tion, referred to as indirectly coupled or nonframe sync loop-
back, has the effect of decoupling the transmission of input data
from the receipt of output data. The delay between receipt of
codec output data and transmission of input data for the codec
is determined by the DSP’s software latency. When program-
ming the DSP serial port for this configuration, it is necessary to
set the Rx FS as an input and the Tx FS as an output generated
by the DSP. This configuration is most useful when operating in
mixed mode, as the DSP has the ability to decide how many
words (either DAC or control) can be sent to the codecs. This
means that full control can be implemented over the device
configuration as well as updating the DAC in a given sample
interval. The second configuration (shown in Figure 11) has the
DSP’s Tx data and Rx data connected to the codec’s SDI and
SDO, respectively while the DSP’s Tx and Rx frame syncs are
connected to the codec’s SDIFS and SDOFS. In this configura-
tion, referred to as directly coupled or frame sync loop-back, the
frame sync signals are connected together and the input data to
the codec is forced to be synchronous with the output data from
the codec. The DSP must be programmed so that both the Tx
FS and Rx FS are inputs as the codec SDOFS will be input to
both. This configuration guarantees that input and output
events occur simultaneously and is the simplest configuration
for operation in normal Data Mode. Note that when program-
ming the DSP in this configuration it is advisable to preload the
Tx register with the first control word to be sent before the
codec is taken out of reset. This ensures that this word will be
transmitted to coincide with the first output word from the
device(s).
Figure 10. Indirectly Coupled or Nonframe Sync Loop-
Back Configuration
Cascade Operation
The AD73422 has been designed to support cascading of extra
external AFEs from either SPORT0 or SPORT1. Cascaded
operation can support mixes of dual or single channel devices with
maximum number of codec units being eight (the AD73422 has
two codec units configured on the device). The SPORT2 inter-
face protocol has been designed so that device addressing is
built into the packet of information sent to the device. This
allows the cascade to be formed with no extra hardware over-
head for control signals or addressing. A cascade can be formed
in either of the two modes previously discussed.
SECTION
DSP
TFS (0/1)
DT (0/1)
SCLK (0/1)
DR (0/1)
RFS (0/1)
AD73422
SDOFS
SCLK2
SDIFS
SDO
SDI
CHANNEL 1
CHANNEL 2
SECTION
AFE
REV. 0