ics87951i-147 Integrated Device Technology, ics87951i-147 Datasheet

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ics87951i-147

Manufacturer Part Number
ics87951i-147
Description
Low Skew, 1-to-9 Differential-tolvcmos Zero Delay Buffer
Manufacturer
Integrated Device Technology
Datasheet
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LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-
LVCMOS ZERO DELAY BUFFER
G
IDT
puts. The single ended clock input accepts LVCMOS or LVTTL
input levels. The CLK1, nCLK1 pair can accept most standard
differential input levels. With output frequencies up to 180MHz,
the ICS87951I-147 is targeted for high performance clock
applications. Along with a fully integrated PLL, the ICS87951I-
147 contains frequency configurable outputs and an external
feedback input for regenerating clocks with “zero delay”.
P
HiPerClockS™
IC S
ENERAL
IN
/ ICS
DIV_SELC
DIV_SELD
DIV_SELA
DIV_SELB
A
EXT_FB
SSIGNMENT
CLK1
GND
V
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
DDA
7mm x 7mm x 1.4mm package body
The ICS87951I-147 is a low voltage, low skew 1-
to-9 Differential-to-LVCMOS/LVTTL Zero Delay
Buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
The ICS87951I-147 has two selectable clock in-
D
1
2
3
4
5
6
7
8
ESCRIPTION
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
ICS87951I-147
32-Lead LQFP
Y package
Top View
24
23
22
21
20
19
18
17
QC0
V
QC1
GND
QD0
V
QD1
GND
DDO
DDO
1
• Fully integrated PLL
• Nine single ended 3.3V or 2.5V LVCMOS/LVTTL outputs
• Selectable single ended CLK0 or
• The single ended CLK0 input can accept the following
• CLK1, nCLK1 supports the following input types:
• Output frequency range: 31.25MHz to 200MHz
• VCO range: 250MHz to 500MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter, RMS: 7ps (maximum)
• Output skew: 270ps (maximum)
• Full 3.3V operating supply at -40°C to 85°C ambient
• Full 2.5V operating supply at 0°C to 85°C ambient
• Available in both standard and lead-free RoHS compliant
F
differential CLK1, nCLK1 inputs
input levels: LVCMOS or LVTTL input levels
LVDS, LVPECL, LVHSTL, SSTL, HCSL
operating temperature
operating temperature
packages
EATURES
ICS87951I-147 REV A JUNE 21, 2006
ICS87951I-147

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ics87951i-147 Summary of contents

Page 1

... LOW SKEW, 1-TO-9 DIFFERENTIAL-TO- LVCMOS ZERO DELAY BUFFER G D ENERAL ESCRIPTION The ICS87951I-147 is a low voltage, low skew to-9 Differential-to-LVCMOS/LVTTL Zero Delay HiPerClockS™ Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87951I-147 has two selectable clock in- puts ...

Page 2

... Internal Pulldown MR/nOE Internal Pulldown DIV_SELD IDT ™ / ICS ™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER 1 0 PHASE VCO DETECTOR 250-500MHz LPF POWER-ON RESET 2 ÷ ÷ ÷ QC0 0 1 QC1 QD0 QD1 0 QD2 1 QD3 QD4 ICS87951I-147 REV A JUNE 21, 2006 ...

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... ICS87951I-147 REV A JUNE 21, 2006 ...

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... ICS87951I-147 REV A JUNE 21, 2006 ...

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... ICS87951I-147 REV A JUNE 21, 2006 ...

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... ICS87951I-147 REV A JUNE 21, 2006 µ ...

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... ICS87951I-147 REV A JUNE 21, 2006 ...

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... Phase Jitter mean t (Ø) = Static Phase Offset mean (where t (Ø) is any random sample, and t (Ø) of the sampled cycles measured on controlled edges ITTER AND TATIC HASE FFSET ICS87951I-147 REV A JUNE 21, 2006 SCOPE Qx 80% 20 the average mean ...

Page 9

... UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87951I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin ...

Page 10

... Ohm nCLK HiPerClockS LVPECL Input 3B CLK/nCLK LOCK 3.3V LVPECL D RIVER 3. Ohm LVDS_Driv er R1 100 Ohm 3D CLK/nCLK LOCK 3.3V LVDS D RIVER ICS87951I-147 REV A JUNE 21, 2006 D NPUT RIVEN BY 3.3V CLK nCLK Receiv er D NPUT RIVEN BY ...

Page 11

... Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS87951I-147 is: 2674 Pin compatible with the MPC951 IDT ™ / ICS ™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER ...

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... ° ICS87951I-147 REV A JUNE 21, 2006 ...

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... ICS87951I-147 REV A JUNE 21, 2006 ° ° ° ° ° ° ° ...

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... ICS87951I-147 REV A JUNE 21, 2006 ...

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... ICS87951I-147 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 netcom@idt.com 408-284-8200 480-763-2056 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Integrated Device Technology, Inc. ...

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