ics87951i-147 Integrated Device Technology, ics87951i-147 Datasheet - Page 9

• Manufacturer Part Number: ics87951i-147
• Description: Low Skew, 1-to-9 Differential-tolvcmos Zero Delay Buffer
• Manufacturer: Integrated Device Technology

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P
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87951I-147 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each V
IDT
W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
OWER
ICS87951I-147
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
IRING THE
™
/ ICS
S
™
DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
UPPLY
D
IFFERENTIAL
F
ILTERING
T
I
NPUT TO
F
ECHNIQUES
IGURE
Single Ended Clock Input
1. S
A
A
DDA
PPLICATION
CCEPT
INGLE
pin.
E
DDA
C1
0.1u
S
NDED
INGLE
V_REF
, and V
S
DD
IGNAL
/2 is
E
DDO
NDED
I
NFORMATION
D
1K
9
R1
1K
R2
RIVING
VDD
L
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
EVELS
CLK
nCLK
D
IFFERENTIAL
F
IGURE
I
NPUT
2. P
V
V
DDO
DDA
OWER
S
DD
.01µF
ICS87951I-147 REV A JUNE 21, 2006
.01µF
UPPLY
= 3.3V, V_REF should be 1.25V
3.3V or 2.5V
F
ILTERING
10Ω
10µF