ics932s421b Integrated Device Technology, ics932s421b Datasheet - Page 20

• Manufacturer Part Number: ics932s421b
• Description: Pcie Gen 2 And Qpi Clock For Intel-based Servers
• Manufacturer: Integrated Device Technology

PD De-assertion
1340D—11/20/08
Comments
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FS_C./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V (-0.3V) then use TEST_SEL
If power-up w/ V<2.0V (-0.3V) then use FS_C
FS_B/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B6b6.
If test mode is invoked by B6b6, only B6b7
is used to select HI-Z or REF/N
FS_B/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
Test Clarification Table
Integrated
Circuit
Systems, Inc.
CPU#, 133MHz
REF, 14.31818
SRC# 100MHz
CPU, 133MHz
SRC, 100MHz
USB, 48MHz
PCI, 33MHz
PD
<1.8mS
Tstable
<300µS, >200mV
Tdrive_PwrDwn#
FS_C/TEST
HW PIN
20
_SEL
0
1
1
1
1
0
0
HW
FS_B/TEST
HW PIN
_MODE
X
X
X
0
0
1
1
ENTRY
TEST
B6b6
BIT
X
X
X
X
0
1
1
SW
REF/N or
B6b7
HI-Z
X
0
1
0
1
0
1
ICS932S421B
NORMAL
OUTPUT
REF/N
REF/N
REF/N
REF/N
HI-Z
HI-Z