ics650-11c Integrated Device Technology, ics650-11c Datasheet
ics650-11c
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ics650-11c Summary of contents
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... Description The ICS650-11C is a low-cost, low-jitter, high-performance clock synthesizer optimized for Alcatel system requirements. Using analog/digital Phase-Locked Loop (PLL) techniques, the device accepts a parallel resonant 17.664 MHz crystal input to produce up to five output clocks. Block Diagram SEL-P SB0:1 SC0:1 X1 17.664 MHz ...
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... Select pin. See table above. Don’t connect. Do not connect this pin to anything. Select pin. See table above. Select pin. See table above. Select pin. Determines frequency of pin 12 per table above. 2 525 Race Street, San Jose, CA 95126 ICS650-11C Alcatel Clock Source Pin 12 33.0 25.0 SC0 Pin 10 ...
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... An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS650-11C. This includes signal traces just underneath the device layers adjacent to the ground plane layer used by the device. ...
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... Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-11C. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied ...
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... Integrated Circuit Systems, Inc. ● Symbol Conditions 25 MHz 33 MHz 80 MHz t 0 2 MHz, at VDD/2 Other clocks, at VDD/2 25/33 MHz, 80 MHz 525 Race Street, San Jose, CA 95126 ICS650-11C Alcatel Clock Source Min. Typ. Max. Units 17.664 MHz 0 -0.05 0.04 -0.04 1.5 1 295 Rev H 102709 www ...
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... SSOP) Symbol SEATING PLANE C .10 (.004) Shipping Packaging Tubes Tape and Reel 6 525 Race Street, San Jose, CA 95126 ICS650-11C Alcatel Clock Source Millimeters Inches Min Max Min Max c L Package Temperature 20-pin SSOP -40 to +85 C 20-pin SSOP -40 to +85 C Rev H 102709 www ...