mpc93h52 Integrated Device Technology, mpc93h52 Datasheet

no-image

mpc93h52

Manufacturer Part Number
mpc93h52
Description
3.3v/ 2.5v Lvcmos 1 11 Clock Generator
Manufacturer
Integrated Device Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mpc93h52AC
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
mpc93h52ACR2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
mpc93h52FA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
IDT™ 3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
3.3 V 1:11 LVCMOS Zero Delay
Clock Generator
Freescale Semiconductor
Technical Data
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V 1:11 LVCMOS Zero Delay
targeted for high performance clock tree applications. With output frequencies up
to 240 MHz and output skews lower than 200 ps the device meets the needs of
most demanding clock applications.
Features
Functional Description
output clock signals of 16.67 to 240 MHz from external clock sources. The internal PLL is optimized for its frequency range and
does not require external lock filter components. One output of the MPC93H52 has to be connected to the PLL feedback input
FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multipli-
cation factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx
pins supporting systems with different but phase-aligned clock frequencies.
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50 Ω transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
MPC93H52 is package in a 32-lead LQFP.
Freescale Confidential Proprietary, NDA Required / Preliminary
The MPC93H52 is a 3.3 V compatible, 1:11 PLL based clock generator
The MPC93H52 is a fully 3.3 V compatible PLL clock generator and clock driver. The device has the capability to generate
The PLL of the MPC93H52 minimizes the propagation delay and, therefore, supports zero-delay applications. All inputs and
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
and 1÷2
applications
32-lead Pb-free Package Available
Configurable 11 outputs LVCMOS PLL clock generator
Fully integrated PLL
Wide range of output clock frequency of 16.67 MHz to 240 MHz
Multiplication of the input reference clock frequency by 3, 2, 1, 3÷2, 2÷3, 1÷3
3.3 V LVCMOS compatible
Maximum output skew of 200 ps
Supports zero-delay applications
Designed for high-performance telecom, networking and computing
32-lead LQFP package
Ambient Temperature Range — 0°C to +70°C
Pin and function compatible to the MPC952
1
32-LEAD LQFP PACKAGE
32-LEAD LQFP PACKAGE
CLOCK GENERATOR
3.3 V LVCMOS 1:11
Pb-FREE PACKAGE
LOW VOLTAGE
CASE 873A-03
CASE 873A-03
FA SUFFIX
AC SUFFIX
DATA SHEET
Rev. 5, 1/2005
MPC93H52
MPC93H52
MPC93H52

Related parts for mpc93h52

mpc93h52 Summary of contents

Page 1

... Pin and function compatible to the MPC952 Functional Description The MPC93H52 is a fully 3.3 V compatible PLL clock generator and clock driver. The device has the capability to generate output clock signals of 16.67 to 240 MHz from external clock sources. The internal PLL is optimized for its frequency range and does not require external lock filter components ...

Page 2

... Figure 1. MPC93H52 Logic Diagram MPC93H52 Figure 2. MPC93H52 32-Lead Package Pinout (Top View) 2 Bank A QA0 ÷ QA1 ÷ QA2 QA3 ÷ 2 QA4 Bank B QB0 1 QB1 0 QB2 QB3 Bank C 1 ...

Page 3

... Outputs disabled (high-impedance state) and reset of the device. During reset, the PLL feedback loop is open and the VCO is operating at its lowest frequency. The MPC93H52 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted ...

Page 4

... I Maximum Quiescent Supply Current CCQ 1. The MPC93H52 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-down resistors affecting the input current the DC current consumption of the device with all outputs open in high impedance state and the inputs in its default state or open. ...

Page 5

... CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f ref 6. See Table 7 and Table 8 for output divider configurations. 7. The MPC93H52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically are within the specified range See application section for part-to-part skew calculation. ...

Page 6

... VCO ÷ 6 33.3- fref is the input clock reference frequency (CCLK). 2. fref is the input clock reference frequency (CCLK). 3. fref is the input clock reference frequency (CCLK). Table 8. MPC93H52 Example Configurations (F_RANGE = 1) (1) PLL fref FSELA Feedback [MHz] (2) VCO ÷ 8 25- ...

Page 7

... MHz QB2 V QB3 CC QC0 200 MHz QC1 MPC93H52 zero-delay (feedback of QB0 = 62.5 MHz). All control pins are left open except FSELC = 1. All outputs are locked in frequency and phase to the input clock. Max Frequency range 120 MHz 120 MHz 120 MHz 240 MHz Figure 4 ...

Page 8

... CMOS fanout buffers. The external feedback option of the MPC93H52 clock driver allows for its use as a zero delay buffer. One example configuration is to use a ÷4 output as a feedback to the PLL and configuring all other outputs to a divide-by-4 mode ...

Page 9

... Figure 9 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC93H52 clock driver is effectively doubled due to its capability to drive multiple lines. IDT™ 3.3 V 1:11 LVCMOS Zero Delay Clock Generator ...

Page 10

... TIME (nS) Figure 10. Single versus Dual Waveforms Pulse Generator Z = 50Ω Figure 12. CCLK MPC93H52 AC Test Reference for V MPC93H52 IDT™ 3.3 V 1:11 LVCMOS Zero Delay Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 10 OutB = 3.9386 D Figure 11. Optimized Dual Line Termination ...

Page 11

... Test Reference mean| JIT(∅ for a controlled edge with respect mean 0 0 Figure 16. I/O Jitter -1/f | JIT( Figure 18. Period Jitter V =3 2.4 0.55 MPC93H52 NETCOM V CC ÷ GND V CC ÷ GND MPC93H52 11 ...

Page 12

... THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. c1 MILLIMETERS DIM MIN MAX A 1.40 1.60 A1 0.05 0. 1.35 1.45 b 0.30 0. 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 D 9.00 BSC D1 7.00 BSC e 0.80 BSC E 9.00 BSC E1 7.00 BSC L 0.50 0.70 L1 1.00 REF q 0˚ 7˚ REF R1 0.08 0.20 R2 0.08 --- S 0.20 REF Advanced Clock Drivers Devices Freescale Semiconductor NETCOM MPC93H52 ...

Page 13

... MPC92459 MPC93H52 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer 3.3 V 1:11 LVCMOS Zero Delay Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. ...

Related keywords