mpc93h52 Integrated Device Technology, mpc93h52 Datasheet - Page 5

• Manufacturer Part Number: mpc93h52
• Description: 3.3v/ 2.5v Lvcmos 1 11 Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93H52
3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Advanced Clock Drivers Devices
Freescale Semiconductor
Table 6. AC Characteristics (V
10. –3 dB point of PLL transfer characteristics.
Symbol
t
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation.
3. The PLL may be unstable with a divide by 2 feedback ratio.
4. In PLL bypass mode, the MPC93H52 divides the input reference clock.
5. The input frequency f
6. See
7. The MPC93H52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t
8. See application section for part-to-part skew calculation.
9. See application section for a jitter calculation for other confidence factors than 1 σ.
t
t
t
t
JIT(PER)
PLZ, HZ
PZL, LZ
JIT(CC)
t
PWMIN
t
t
f
f
JIT(∅)
LOCK
t
sk(O)
t
BW
VCO
MAX
t
DC
f
r
r
(∅)
t
ref
, t
, t
r
/t
f
f
f
are within the specified range.
Table 7
Input reference frequency
in PLL mode
Input reference frequency in PLL bypass mode
VCO lock frequency range
Output Frequency
Minimum Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation Delay CCLK to FB_IN
(static phase offset)
Output-to-output Skew
Output duty cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidth
Maximum PLL Lock Time
and
Table 8
(2) (3)
ref
(9)
on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: f
for output divider configurations.
Characteristics
(8)
CC
÷12 feedback divider RMS (1 σ)
÷4 feedback divider RMS (1 σ)
÷6 feedback divider RMS (1 σ)
÷8 feedback divider RMS (1 σ)
(5)
(7)
(10)
= 3.3 V ± 5%, T
all outputs same frequency
all outputs same frequency
all outputs, any frequency
output frequencies mixed
output frequencies mixed
within QC output bank
within QA output bank
within QB output bank
(f
÷12 feedback
÷12 feedback
ref
÷4 feedback
÷6 feedback
÷8 feedback
÷4 feedback
÷6 feedback
÷8 feedback
÷2 output
A
÷12 output
= 50 MHz)
(4)
÷4 output
÷6 output
÷8 output
= 0° to 70°C)
(6)
5
TT
.
(1)
16.67
16.67
–200
50.0
33.3
25.0
50.0
33.3
Min
200
100
2.0
0.1
50
25
45
2.0–8.0
1.0–4.0
0.8–2.5
0.6–1.5
Typ
50
40
40
40
40
120.0
250.0
+200
Max
80.0
60.0
40.0
480
240
120
300
200
200
100
150
1.0
1.0
80
60
40
55
10
25
75
20
10
8
(∅)
, can only be guaranteed if
ref
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ns
ns
ps
ps
ps
ps
ps
ps
%
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
= f
VCO
0.8 to 2.0 V
PLL locked
0.55 to 2.4 V
RMS
RMS
RMS
RMS
÷ FB.
Condition
MPC93H52
NETCOM
MPC93H52
5