mpc9855 Integrated Device Technology, mpc9855 Datasheet - Page 5

• Manufacturer Part Number: mpc9855
• Description: Xtal-input, Lvcmos Input, 8 Lvcmos Output Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9855
Clock Generator for PowerQUICC III
Advanced Clock Drivers Devices
Freescale Semiconductor
Output Frequency Configuration
used frequencies in PowerQUICC, PowerPC and other
microprocessor systems.
values that will generate those common frequencies. The
MPC9855 can generate numerous other frequencies that
may be useful in specific applications. The output frequency
(f
following equation.
where f
Note that N = 15 is a modified case of the configuration inputs
Power Supply Bypassing
architecture of the MPC9855 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all V
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
out
The MPC9855 was designed to provide the commonly
This calculation is valid for all values of N from 8 to 126.
The MPC9855 is a mixed analog/digital product. The
) of either Bank A or Bank B may be calculated by the
V
out
DD
is in MHz and N = 2 * CLK_x[0:5]
Figure 3. V
DD
15 Ω
pins should be bypassed by
CC
f
out
22 µF
Table 3
Power Supply Bypass
= 2000 / N
V
MR
0.1 µF
DD
0.1 µF
lists the configuration
t
reset_rel
V
V
DD
DDA
OPERATION INFORMATION
MPC9855
Figure 2. MR Operation
5
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
00111 or 7.
Crystal Input Operation
Power-Up and MR Operation
length for MR pin. The MR release time is based upon the
power supply being stable and within V
Table 9
configured after release of reset and the outputs will be stable
for use after lock is obtained.
MPC9855 can be calculated as follows.
where
Power Consumption Calculation
TBD
Figure 2
For unloaded outputs the power consumption of the
P = V
V
I
n
n
V
V
C
f
f
DDBASE
A
B
A
B
DD
DDOA
DDOB
PD
= frequency of bank A outputs
= frequency of bank B outputs
= number of A bank outputs (= 4)
= number of B bank outputs (= 4)
+ n
= core supply voltage
= power dissipation capacitance
DD
for actual parameter values. The MPC9855 may be
B
= voltage supply on bank A outputs
= voltage supply on bank B outputs
* (V
= base supply current
* I
defines the release time and the minimum pulse
DDBASE
DDOB
** 2 * C
t
+ n
reset_pulse
A
* (V
PD
DDOA
* f
B
)
** 2 * C
DD
specifications. See
PD
* f
A
)
MPC9855
NETCOM
MPC9855
5