sy89425jctr Micrel Semiconductor, sy89425jctr Datasheet

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sy89425jctr

Manufacturer Part Number
sy89425jctr
Description
Dual Sonet Oc-12 Clock Synthesizer
Manufacturer
Micrel Semiconductor
Datasheet
CLOCK IN
TYPICAL APPLICATION
FEATURES
Two independently-powered 622.08MHz clock
sources one chip
Differential PECL outputs
TTL/CMOS compatible inputs
SONET compliant jitter performance ( 0.01UI)
Choice of three reference frequencies for each PLL
Only 395mW per PLL (typ)
Complies with Bellcore, CCITT and ANSI standards
Single +5 volt power supply
Fully compatible with industry standard 10KH I/O
levels
Available in 28-pin PLCC package
0.1uF
500
FLTRAN
SEL39A
(TTL)
SEL78A
(TTL)
FLTRAP
RFCKA
(TTL)
GND
GND
(SAME AS PLL A)
VCCA
+5V
PLL B
PLL A
VCCOA
+5V
AGND
CK622AN
CK622AP
(PECL)
RSTA
(TTL)
+3V
DUAL SONET OC-12
CLOCK SYNTHESIZER
2X 50
622.08MHz
1
(PLL) consists of two totally separate, SONET compliant
622.08MHz clock generators on one chip. The user may
select to power both PLLs or PLL A only. Each PLL
produces a low-jitter OC-12/STS-12 clock rate from an
input reference clock of 38.88, 51.84, or 77.76MHz. When
using both PLLs, it is not necessary that they share a
common reference clock (e.g., PLL A may operate from an
STS-1 reference of 51.84MHz, while PLL B operates from
an OC-3/STS-3 reference of 77.76MHz).
requires only a simple series RC loop filter for each PLL.
with our proprietary ASSET™ bipolar process has produced
a clock generator IC which exceeds applicable Bellcore
and ANSI specifications, while setting a new standard for
performance and flexibility.
DESCRIPTION
PIN CONFIGURATION
Micrel-Synergy's SY89425 Dual Phase Locked Loop
The SY89425 operates from a single +5 volt supply, and
Coupling Micrel-Synergy's advanced PLL technology
SEL39A
SEL78A
SEL78B
SEL39B
RFCKA
RFCKB
V
CCA
26
27
28
2
3
4
1
25 24 23 22 21 20 19
5
6
TOP VIEW
7
PLCC
8
9
10 11
ClockWorks™
18
17
16
15
14
13
12
Rev.: E
Issue Date: August, 1998
CK622AP
CK622AN
CK622BN
CK622BP
V
GND
V
CCOA
CCOB
SY89425
Amendment: /0

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sy89425jctr Summary of contents

Page 1

FEATURES Two independently-powered 622.08MHz clock sources one chip Differential PECL outputs TTL/CMOS compatible inputs SONET compliant jitter performance ( 0.01UI) Choice of three reference frequencies for each PLL Only 395mW per PLL (typ) Complies with Bellcore, CCITT and ANSI standards ...

Page 2

Micrel FUNCTIONAL BLOCK DIAGRAM RFCKA (TTL) SEL39A (TTL) SEL78A (TTL) SEL78B (TTL) SEL39B (TTL) RFCKB (TTL) GND FLTRAP/N V CCA 2 3 CHG /f PUMP FEEDBACK DIVIDER (8/12/16) FEEDBACK DIVIDER (8/12/16) CHG /f PUMP 3 2 GND FLTRBP/N V CCB ...

Page 3

Micrel PIN DESCRIPTION INPUTS RFCKB [Reference Clock B] TTL Reference clock in for PLL B. (38.88, 51.84 or 77.76MHz). SEL39B [38.88MHz Select B] TTL Logic HIGH on this pin denotes a 38.88MHz input reference clock for PLL B. Tie to ...

Page 4

Micrel PECL DC ELECTRICAL CHARACTERISTIC +5V CCA CCB CCOA CCOB Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL (1) V Input HIGH Voltage IH (1) V Input LOW Voltage ...

Page 5

Micrel AC ELECTRICAL CHARACTERISTICS +5V 5%; GND = 0V; T CCA CCB CCOA CCOB Parameter VCO Center Frequency Reference Clock (RFCK) Frequency Tolerance Reference Clock (RFCK) Input Duty Cycle Acquisition Lock Time TTL ...

Page 6

... PRODUCT ORDERING CODE Ordering Package Code Type SY89425JC J28-1 SY89425JCTR J28-1 Jitter Generation Requirement Bellcore TA-NWT-000253 (Issue 2), section 5.6.5.2 "For Category II interfaces, jitter generation shall not exceed 0.01 UI rms. For OC-N and STSX-N interfaces, a high-pass measurement filter with a 12kHz cutoff frequency shall be used." The low-pass cutoff frequency of the measurement filter shall be higher than 5MHz ...

Page 7

Micrel 28 LEAD PLCC (J28-1) 7 ClockWorks™ SY89425 Rev. 03 ...

Page 8

Micrel MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 TEL This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents ...

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