sy89113u Micrel Semiconductor, sy89113u Datasheet

sy89113u

Manufacturer Part Number

sy89113u

Description

Sy89113u 2.5v Low Jitter, Low Skew 1 12 Lvds Fanout Buffer With 2 1 Input Mux And Internal Termination

Manufacturer

Micrel Semiconductor

Datasheet

1.SY89113U.pdf (14 pages)

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December 2007

General Description

The SY89113U is a 2.5V low jitter, low skew, 1:12

LVDS fanout buffer optimized for precision telecom

and enterprise server distribution applications. The

input includes a 2:1 MUX for clock switchover

applications. Unlike other multiplexers, this input

includes a unique isolation design that minimizes

channel-to-channel

distributes clock frequencies from DC to >1GHz

guaranteed over temperature and voltage. The

SY89113U incorporates a synchronous output enable

(EN) so that the outputs will only be enabled/disabled

when they are already in the LOW state.

CLK0 differential input includes Micrel's unique, 3-pin

input termination architecture that directly interfaces to

any differential signal (AC- or DC-coupled) as small as

100mV (200mV

termination resistor networks in the signal path.

CLK1 differential input includes a new version of

Micrel's unique, Any-Input architecture that directly

interfaces

(including

differential (AC- or DC-coupled) LVDS, HSTL, CML,

and LVPECL logic levels as small as 200mV

(400mV

LVDS output swing 325mV into 100Ω with extremely

fast rise/fall time guaranteed to be less than 250ps.

The SY89113U operates from a 2.5V±5% supply and

is guaranteed over the full industrial temperature

range of -40°C to +85°C. The SY89113U is part of

Micrel's high-speed, Precision Edge

All support documentation can be found on Micrel’s

web site at:

Precision Edge is a registered trademark of Micrel, Inc.

MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

). CLK1 input requires external termination.

3.3V

www.micrel.com.

with

) without any level shifting or

single-ended

logic),

crosstalk.

single-ended

TTL/CMOS

The

product line.

SY89113U

LVPECL,

logic

Fanout Buffer with 2:1 Input MUX and

2.5V Low Jitter, Low Skew 1:12 LVDS

Features

• Selects between 1 of 2 inputs, and provides 12

• Guaranteed AC performance over temperature and

• Ultra-low jitter design:

• Unique, patent-pending 2:1 input MUX provides

• CLK0 input features a unique, patent-pending input

• CLK1 accepts virtually any logic standard:

• 325mV LVDS-compatible output swing

• Power supply: 2.5V +5%

• Industrial temperature range –40°C to +85°C

• Available in 44-pin (7mm x 7mm) MLF

Applications

• Multi-processor server

• SONET/SDH clock/data distribution

• Fibre Channel distribution

• Gigabit Ethernet clock distribution

precision, low skew LVDS output copies

voltage:

– DC to >1GHz throughput

– <975ps propagation delay CLK0-to-Q

– <250ps rise/fall time

– <25ps output-to-output skew

– <1ps

– <10ps

– <1ps

– <0.7ps

superior isolation to minimize channel-to-channel

crosstalk

termination and VT pin that accepts AC- and DC-

coupled inputs (CML, LVPECL, LVDS)

– Single-ended: TTL/CMOS (including 3.3V logic),

– Differential: LVPECL, LVDS, CML, HSTL

LVPECL

Internal Termination

RMS

SY89113U

cycle-to-cycle jitter

total jitter (clock)

random jitter

crosstalk induced jitter

hbwhelp@micrel.com

Precision Edge

or (408) 955-1690

M9999-120607

package

Related parts for sy89113u

sy89113u Summary of contents

Page 1

... The SY89113U operates from a 2.5V±5% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89113U is part of Micrel's high-speed, Precision Edge All support documentation can be found on Micrel’s web site at: www ...

Page 2

Functional Block Diagram December 2007 2 hbwhelp@micrel.com M9999-120607 or (408) 955-1690 ...

Page 3

... Truth Table Note: 1. Transition occurs on next negative transition of the non-inverted input. December 2007 Operating Package Marking Range Industrial SY89113U with Pb-Free bar-line indicator Industrial SY89113U with Pb-Free bar-line indicator = 25°C, DC Electricals only. A ® 44-Pin MLF (MLF-44) CLK_SEL Q L CLK0 H CLK1 (1) X ...

Page 4

Pin Description Pin Number Pin Name GND 11, 22, 34 Exposed Pad CLK0, /CLK0 VT0 4 VREF-AC0 7 SE-TERM 8, 10 CLK1, /CLK1 9 VBB1 12 EN 13, 23, 28, VCC 33 CLK_SEL ...

Page 5

Absolute Maximum Ratings Supply Voltage (V ) .......................... –0.5V to +4.0V CC Input Voltage (Differential Input CLK0, CLK1 Current on Reference Voltage Outputs Source or sink current on VREF-AC0, VBB1.....±2mA Termination Current Source or sink current on VT0 ................±100mA Input ...

Page 6

LVDS Outputs DC Electrical Characteristics V = +2.5V ±5 –40°C to +85° Symbol Parameter V Output Voltage Swing OUT Differential Output Voltage Swing DIFF-OUT Output Common Mode Voltage OCM ...

Page 7

AC Electrical Characteristics V = +2.5V ±5 –40° 85° Symbol Parameter f Maximum Operating Frequency MAX Propagation Delay CLK0-to CLK1-to-Q CLK_SEL-to-Q t Differential Propagation Delay Temperature PD Tempco Coefficient Set-up Time ...

Page 8

Typical Operating Characteristics V = 2.5V, GND = 400mV Functional Characteristics V = 2.5V, GND = 400mV December 2007 = 100Ω across the output pair ...

Page 9

Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing CLK0 Timing Diagrams /CLK CLK /Q Q CLK_SEL / /CLK CLK /Q Q December 2007 Figure 1b. Differential Voltage Swing CLK0 t PD Differential In-to-Differential Out ...

Page 10

Input and Output Stages Figure 2a. CLK1 Differential Input Structure CLK0 Input Interface Applications Figure 3a. LVPECL Interface (DC-Coupled) Figure 3d. CML Interface (AC-Coupled) December 2007 Figure 2b. CLK0 Differential Input Structure Figure 3b. LVPECL Interface (AC-Coupled) Figure 3e. LVDS ...

Page 11

CLK1 Input Interface Applications Figure 4a. CML, LVDS Interface (DC-Coupled) Figure 4d. PECL Interface (AC-Coupled) December 2007 Figure 4b. CML Interface (DC-Coupled) Figure 4e. PECL Interface (Single-Ended) 11 Figure 4c. PECL Interface (DC-Coupled) (See Single-Ended TTL/CMOS Recommended Resistor Table for ...

Page 12

... Single-Ended TTL/CMOS Recommended Resistor Value The SY89113U can be driven by a TTL/CMOS input signal. See Figure 4f. The resistor R, in Table 1, below is calculated according to the following equation: ⎡ ⎢ 1 ⎢ 1.594 × 5.057 × V ⎢ ⎢ 2 × ⎣ The equation above is used to determine the optimum value of R for best duty cycle. Recommended R (Ω ...

Page 13

Package Information Package Notes: 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry pack form. 2. Exposed pads must be soldered to a ground for proper thermal management. December 2007 44-Pin MLF™ (MLF-44) ® 44-Pin MLF ...

Page 14

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is ...

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