sy87700v Micrel Semiconductor, sy87700v Datasheet - Page 4

• Manufacturer Part Number: sy87700v
• Description: Sy87700v 5v/3.3v 32-175mbps Anyrate Clock And Data Recovery
• Manufacturer: Micrel Semiconductor

Micrel, Inc.
Clock Recovery
a clock that is at the same frequency as the incoming data
bit rate at the Serial Data input. The clock is phase aligned
by a PLL so that it samples the data in the center of the
data eye pattern.
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30 s data stream of continuous
1’s or 0’s for random incoming NRZ data.
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
M9999-073008
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FUNCTIONAL DESCRIPTION
Clock Recovery, as shown in the block diagram generates
The phase relationship between the edge transitions of
Frequency stability without incoming data is guaranteed
The loop filter transfer function is optimized to enable the
The total loop dynamics of the clock recovery PLL
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Lock Detect
monitors the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be forced to
lock to the local reference clock. This will maintain the correct
frequency of the recovered clock output under loss of signal
or loss of lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by more
than approximately 1000ppm, the PLL will be declared out
of lock. The lock detect circuit will poll the input data stream
in an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within approximately
1000ppm, the PLL will be declared in lock and the lock
detect output will go active.
The SY87700V contains a link fault indication circuit which
SY87700V