mc100ep196a ON Semiconductor, mc100ep196a Datasheet
mc100ep196a
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mc100ep196a Summary of contents
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... D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 3. The IN/IN inputs can accept LVPECL (SE of Diff), or LVDS level signals. Because the MC100EP196A is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for controlling Pins 14 and 15, CASCADE and CASCADE, also latched by LEN, in cascading multiple PDCs for increased programmable range ...
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... MC100EP196A D10 Figure 1. 32−Lead QFN (Top View) http://onsemi.com FTUNE 15 16 Exposed Pad (EP) ...
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... SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs. 2. All V and V pins must be externally connected to Power Supply to guarantee proper operation MC100EP196A Default State Low Single−Ended Parallel Data Inputs [0:9]. Internal (Note 1) Low Single−Ended CASCADE/CASCADE Control Input. Internal ...
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... Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 6. For additional information, see Application Note AND8003/D. MC100EP196A Input Signal is Propagated to the Output Output Holds Logic Low State Transparent or LOAD mode for real time delay values present on D[0:10]. ...
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... MC100EP196A Figure 2. Logic Diagram http://onsemi.com 5 ...
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... XXXXXXXXXX *Fixed minimum delay not included. Table 7. TYPICAL FTUNE DELAY PIN Input Range V −V ( MC100EP196A SETMIN SETMAX ...
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... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MC100EP196A 300 400 500 600 Decimal Value of Select Inputs (D[9:0]) Figure 3 ...
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... Input and output parameters vary 1:1 with V 8. All loading with − 2 min varies 1:1 with IHCMR EE IHCMR input signal. MC100EP196A (Note −40°C Min Typ Max 100 135 ...
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... Required 500 lfpm air flow when using +5 V power supply. For (V protection at elevated temperatures. Recommend V 12. All loading with − 2 13. V min varies 1:1 with IHCMR EE IHCMR input signal. MC100EP196A −3.3 V (Note 10 −40°C Min Typ Max Min 100 ...
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... This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified propagation delay and transition times. 21. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps. MC100EP196A = −3 −3 3 3.6 V ...
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... E196A. Obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay. Figure 6 illustrates the interconnect scheme for cascading two EP196As. As can be seen, this scheme can easily be MC100EP196A ...
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... Need if Chip #3 is used D10 EP196A IN INPUT IN CHIP # MC100EP196A A11 A10 D10 Figure 6. Cascading Interconnect Architecture http://onsemi ...
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... MIN SET MAX Figure 7. Expansion of the Latch Section of the EP196A Block Diagram MC100EP196A (1111111111 on the A0—A9 address bus) D10 will be asserted to signal the need to cascade the delay to the next EP196A device. When D10 is asserted, the SET MIN pin of chip #2 will be deasserted and SET MAX pin asserted resulting in the device delay to be the maximum delay ...
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... MC100EP196A ...
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... Control Logic Figure 9. Multiple Channel Deskewing Diagram MC100EP196A be sent through each EP196A as shown in Figure 8. One signal channel can be used as reference and the other EP196As can be used to adjust the delay to eliminate the timing skews. Nearly any high−speed system can be fine−tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances ...
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... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100EP196AMNG MC100EP196AMNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MC100EP196A = ...
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... MC100EP196A Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1642/D − The ECL Translator Guide AND8001/D − ...
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... BSC D2 2.950 3.100 3.250 E 5.00 BSC E2 2.950 3.100 3.250 e 0.500 BSC K 0.200 −−− −−− L 0.300 0.400 0.500 5.30 3.20 3.20 5. 0.50 PITCH DIMENSIONS: MILLIMETERS ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100EP196A/D ...