mc100ep446 ON Semiconductor, mc100ep446 Datasheet - Page 12

• Manufacturer Part Number: mc100ep446
• Description: 3.3v/5v 8??bit Cmos/ecl/ttl Data Input Parallel/serial Converter
• Manufacturer: ON Semiconductor

converter. An attribute for EP446 is that the parallel inputs
D0–D7 (Pins 17 – 24) can be configured to accept either
CMOS, ECL, or TTL level signals by a combination of
interconnects between V
For CMOS input levels, leave V
operation, short V
operation, connect a 1.5 V supply reference to V
the V
be accomplished by placing a 1.5 kW or 500 W between V
and V
The MC10/100EP446 is an integrated 8:1 parallel to serial
CKSEL
SOUT
PCLK
EF
CLK
EE
D0
D1
D2
D3
D4
D5
D6
D7
pin open. The 1.5 V reference voltage to V
for 3.3 V or 5.0 V power supplies, respectively.
CF
Data Latched
Figure 7. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW
and V
EF
À
D1−1
D0−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
(Pin 27) and V
Number of Clock Cycles from Data Latch to SOUT
EF
1
(Pins 26 and 27). For TTL
EF
and V
2
CF
CF
3
open. For ECL
APPLICATION INFORMATION
(Pin 26) pins.
CF
Data Latched
CF
4
and leave
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pin can
D1−2
D0−2
D2−2
D3−2
D4−2
D5−2
D6−2
D7−2
CF
5
12
6
Note: all pins requiring ECL voltage inputs must have a
50 W terminating resistor to V
select the serial data rate output between internal clock data
rate or twice the internal clock data rate. For CKSEL LOW
operation, the time from when the parallel data is latched ¬
to when the data is seen on the S
of the 7
(Figure 7). Note the PCLK switches on the falling edge of
CLK.
The CKSEL input (Pin 2) is provided to enable the user to
Á
7
th
Data Latched
clock cycle plus internal propagation delay
D0−3
D1−3
D2−3
D3−3
D4−3
D5−3
D6−3
D7−3
TT
OUT
(V
­ is on the falling edge
TT
Data Latched
= V
CC
– 2.0 V).
D0−4
D1−4
D2−4
D3−4
D4−4
D5−4
D6−4
D7−4