mc100lvep210 ON Semiconductor, mc100lvep210 Datasheet

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mc100lvep210

Manufacturer Part Number
mc100lvep210
Description
Low-voltage 1 5 Dual Diff.lvecl/lvpecl/lvepecl/hstl Clock Driver
Manufacturer
ON Semiconductor
Datasheet
MC100LVEP210
2.5V / 3.3V 1:5 Dual
Differential ECL/PECL/HSTL
Clock Driver
Description
The MC100LVEP210 is a low skew 1-to-5 dual differential driver,
designed with clock distribution in mind. The ECL/PECL input
signals can be either differential or single-ended if the V
used. The signal is fanned out to 5 identical differential outputs. HSTL
inputs can be used when the EP210 is operating in PECL mode.
The LVEP210 specifically guarantees low output-to-output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure the tight skew specification is realized, both sides of the
differential output need to be terminated identically into 50 W even if
only one output is being used. If an output pair is unused, both outputs
may be left open (unterminated) without affecting skew.
The MC100LVEP210, as with most other ECL devices, can be
operated from a positive V
supply in PECL mode. This allows the
CC
LVEP210 to be used for high performance clock distribution in +3.3 V
or +2.5 V systems. Single-ended CLK input operation is limited to a
≥ 3.0 V in PECL mode, or V
V
CC
EE
Designers can take advantage of the LVEP210's performance to
distribute low skew clocks across the backplane or the board. In a
PECL environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For more
information on using PECL, designers should refer to Application
Note AN1406/D.
Features
85 ps Typical Device-to- Device Skew
20 ps Typical Output-to-Output Skew
V
Output
BB
Jitter Less than 1 ps RMS
350 ps Typical Propagation Delay
Maximum Frequency u 3 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode Operating Range: V
with V
= 0 V
EE
NECL Mode Operating Range: V
CC
with V
= -2.375 V to -3.8 V
EE
Open Input Default State
LVDS Input Compatible
Fully Compatible with MC100EP210
Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2007
August, 2007 - Rev. 13
output is
BB
≤ -3.0 V in ECL mode.
= 2.375 V to 3.8 V
CC
= 0 V
1
http://onsemi.com
MARKING
DIAGRAMS*
MC100
LVEP21
AWLYYWWG
32-LEAD LQFP
FA SUFFIX
CASE 873A
1
MC100
LVEP210
1
32
AWLYYWWG
QFN32
G
MN SUFFIX
CASE 488AM
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Publication Order Number:
MC100LVEP210/D

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mc100lvep210 Summary of contents

Page 1

... W even if only one output is being used output pair is unused, both outputs may be left open (unterminated) without affecting skew. The MC100LVEP210, as with most other ECL devices, can be operated from a positive V supply in PECL mode. This allows the CC LVEP210 to be used for high performance clock distribution in +3 ...

Page 2

... Qa2 Qa3 V BB Qa3 V Qa4 Qa4 Figure 3. Logic Diagram http://onsemi.com 2 Exposed Pad (EP Qa3 23 Qa3 22 Qa4 Qa4 21 MC100LVEP210 Qb0 20 Qb0 19 Qb1 18 Qb1 Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 Qb3 Qb3 Qb4 Qb4 ...

Page 3

... Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MC100LVEP210 Characteristics Human Body Model Machine Model ...

Page 4

... Input and output parameters vary 1:1 with V 6. All loading with 2 Single-ended input operation is limited min varies 1:1 with IHCMR EE IHCMR input signal. MC100LVEP210 (Note -40 °C Min Typ Max Min 55 70 ...

Page 5

... Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. MC100LVEP210 ...

Page 6

... Skew is measured between outputs under identical transitions of similar paths through a device. 15. Device-to-Device skew for identical transitions at identical V 800 700 600 500 400 300 200 100 0 0 MC100LVEP210 = -2.375 to -3 2.375 to 3 -40 °C Min Typ Max 3 220 ...

Page 7

... Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVEP210FA MC100LVEP210FAG MC100LVEP210FAR2 MC100LVEP210FARG MC100LVEP210MNG MC100LVEP210MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D ...

Page 8

... DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MC100LVEP210 PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A-02 ISSUE C 4X 0.20 (0.008) AB ...

Page 9

... A3 0.200 REF b 0.180 0.250 0.300 D 5.00 BSC D2 2.950 3.100 3.250 E 5.00 BSC E2 2.950 3.100 3.250 e 0.500 BSC K 0.200 --- --- L 0.300 0.400 0.500 5.30 3.20 3.20 5. 0.50 PITCH ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100LVEP210/D ...

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