mc88915 Integrated Device Technology, mc88915 Datasheet - Page 6

• Manufacturer Part Number: mc88915
• Description: Low Skew Cmos Pll Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
Table 8. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations
MC88915
LOW SKEW CMOS PLL CLOCK DRIVERS
GENERAL AC SPECIFICATION NOTES
1.
2.
4.
FREQ_SEL
Statistical characterization techniques were used to
guarantee those specifications which cannot be
measured on the ATE. MC88915 units were fabricated
with key transistor properties intentionally varied to
create a 14-cell designed experimental matrix. IC
performance was characterized over a range of
transistor properties (represented by the 14 cells) in
excess of the expected process variation of the wafer
fabrication area. In this way all units passing the ATE
test will meet or exceed the non-tested specifications
limits.
These two specs (t
output) guarantee the MC88915 meets the 25 MHz
MC68040 P-Clock input specification (at 50 MHz). For
A 1 MΩ resistor tied to either Analog V
GND, depicted in
is present on the MC88915 outputs. This technique
causes a phase offset between the SYNC input and the
output connected to the FEEDBACK input, measured at
the input pins. The t
varies with process, temperature, and voltage. The
specs were determined by measuring the phase
Level
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Any “Q” (Q0–Q4)
Any “Q” (Q0–Q4)
Feedback
Figure
Output
RISE/FALL
2X_Q
2X_Q
PD
Q/2
Q/2
Q5
Q5
2X_Q OUTPUT
spec describes how this offset
88915
4, is required to ensure no jitter
and t
Figure 3. MC68040 P-Clock Input Termination Scheme
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
2.5 to (2X_Q FMAX Spec)/8
5 to (2X_Q FMAX Spec)/4
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
PULSE
R
S
Frequency Range (MHz)
CC
= Z
Allowable SYNC Input
Width 2X_Q
R
or Analog
O
S
– 7 Ω
Z
O
(CLOCK TRACE)
6
3.
R
these two specs to be guaranteed by Freescale
Semiconductor, the termination scheme shown below in
Figure 3
The wiring diagrams and explanations in
demonstrate the input and output frequency
relationships for three possible feedback configurations.
The allowable SYNC input range for each case is also
indicated. There are two allowable SYNC frequency
ranges, depending whether FREQ_SEL is high or low.
Although not shown, it is possible to feed back the Q5
output, thus creating a 180° phase shift between the
SYNC input and the “Q” outputs.
summarizes the allowable SYNC frequency range for
each possible configuration.
relationship for the 14 lots described in Note 1 while the
part was in phase-locked operation. The actual
measurements were made with a 10 MHz SYNC input
(1.0 ns edge rate from 0.8 V – 2.0 V) with the Q/2 output
fed back. The phase measurements were made at
1.5 V. The Q/2 output was terminated at the
FEEDBACK input with 100 Ω to V
ground.
P
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
Corresponding VCO
Frequency Range
R
must be used.
P
= 1.5 Z
P-CLOCK INPUT
O
68040
to Rising SYNC Edge
Phase Relationships
Table 8
of the “Q” Outputs
MC88915 REV 6 JULY 10, 2007
CC
and 100 Ω to
180°
180°
Figure 7
below
0°
0°
0°
0°
0°
0°