sy100e111aejytr Micrel Semiconductor, sy100e111aejytr Datasheet

sy100e111aejytr

Manufacturer Part Number

sy100e111aejytr

Description

Sy10/100e111ae/le 5v/3.3v 1 9 Differential Clock Driver W/enable

Manufacturer

Micrel Semiconductor

Datasheet

1.SY100E111AEJYTR.pdf (6 pages)

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Micrel, Inc.

Precision Edge is a registered trademark of Micrel, Inc.

M9999-032006

hbwhelp@micrel.com or (408) 955-1690

PIN NAMES

FEATURES

5V and 3.3V power supply options

200ps part-to-part skew

50ps output-to-output skew

Differential design

Enable Input

Voltage and temperature compensated outputs

75K input pulldown resistors

Fully compatible with Motorola MC10/100E111

Available in 28-pin PLCC package

BLOCK DIAGRAM

IN, IN

CCO

, Q

output

— Q

, Q

Differential Input Pair

Enable Input

Differential Outputs

Output

to Output

Function

5V/3.3V 1:9 DIFFERENTIAL

CLOCK DRIVER (w/ENABLE)

drivers designed for clock distribution in mind. The SY10/

100E111AE/LE's function and performance are similar to

the popular SY10/100E111, with the improvement of lower

jitter and the added feature of low voltage operation. It

accepts one signal input, which can be either differential or

single-ended if the V

out to 9 identical differential outputs. An enable input is

also provided such that a logic HIGH disables the device by

forcing all Q outputs LOW and all Q outputs HIGH.

produced with low skew as the key goal. Optimal design

and layout serve to minimize gate to gate skew within a

device, and empirical modeling is used to determine process

control limits that ensure consistent t

lot to lot. The net result is a dependable, guaranteed low

skew device.

necessary that both sides of the differential output are

terminated into 50 , even if only one side is being used. In

most applications, all nine differential pairs will be used

and therefore terminated. In the case where fewer that

nine pairs are used, it is necessary to terminate at least the

output pairs on the same package side as the pair(s) being

used on that side, in order to maintain minimum skew.

Failure to do this will result in small degradations of

propagation delay (on the order of 10-20ps) of the output(s)

being used which, while not being catastrophic to most

designs, will mean a loss of skew margin.

be operated from a positive V

This allows the E111AE/LE to be used for high performance

clock distribution in +5V/+3.3V systems. Designers can

take advantage of the E111AE/LE's performance to

distribute low skew clocks across the backplane or the

board. In a PECL environment, series or Thevenin line

terminations are typically used as they require no additional

power supplies. For systems incorporating GTL, parallel

termination offers the lowest power by taking advantage of

the 1.2V supply as terminating voltage.

DESCRIPTION

The SY10/100E111AE/LE are low skew 1-to-9 differential

The E111AE/LE is specifically designed, modeled and

To ensure that the tight skew specification is met it is

The E111AE/LE, as with most other ECL devices, can

output is used. The signal is fanned

SY100E111AE/LE

supply in PECL mode.

SY10E111AE/LE

Precision Edge

Rev.: G

Rev. Date:

Precision Edge

distributions from

SY100E111AE/LE

Precision Edge

SY10E111AE/LE

Amendment: /0

March 2006

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sy100e111aejytr Summary of contents

Page 1

Micrel, Inc. FEATURES 5V and 3.3V power supply options 200ps part-to-part skew 50ps output-to-output skew Differential design V output BB Enable Input Voltage and temperature compensated outputs 75K input pulldown resistors Fully compatible with Motorola MC10/100E111 Available in 28-pin PLCC ...

Page 2

... SY10E111LEJCTR J28-1 SY100E111LEJC J28-1 (2) SY100E111LEJCTR J28-1 (3) SY10E111AEJY J28-1 (2, 3) SY10E111AEJYTR J28-1 (3) SY100E111AEJY J28-1 (2, 3) SY100E111AEJYTR J28-1 (3) SY10E111LEJY J28-1 (2, 3) SY10E111LEJYTR J28-1 (3) SY100E111LEJY J28-1 (2, 3) SY100E111LEJYTR J28-1 Notes: 1. Contact factory for die availability. Dice are guaranteed Tape and Reel. 3. Pb-Free package is recommended for new designs. ...

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